DVCon Sponsored Workshop: Verification of Inferencing Algorithm Accelerators

DVCon Sponsored Workshop: Verification of Inferencing Algorithm Accelerators
by Admin on 01-25-2023 at 2:32 pm

This short workshop will cover the verification of a custom AI accelerator as it is migrated from a machine learning framework in Python to RTL. Using High-Level synthesis provides a C++ version of the algorithm being verified. We will show how the original Python can be verified, and subsequent implementations, C++ and RTL, can… Read More


Optimized Chip Design with Main Processors and AI Accelerators

Optimized Chip Design with Main Processors and AI Accelerators
by Admin on 01-26-2022 at 12:19 pm

Feb 15 2022, 10:00am PST

Presented by

Paul Karazuba, VP of Marketing, Expedera & John Min, Director of Field Application Engineering, Andes Technology

About this talk

As the use of AI is beginning large-scale deployment into our devices, many wonder why specialized AI accelerator is employed, rather
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Using eFPGA to Dynamically Adapt to Changing Workloads

Using eFPGA to Dynamically Adapt to Changing Workloads
by Kalar Rajendiran on 04-22-2021 at 10:00 am

Dynamic Reconfig Not New Why Now FlexLogix

In early April, Gabriele Saucier kicked off Design & Reuse’s IPSoC Silicon Valley 2021 Conference. IPSoC conference as the name suggests is dedicated to semiconductor intellectual property (IP) and IP-based electronic systems. There were a number of excellent presentations at the conference. The presentations had been… Read More