Tuning Analog IP for High Yield at SMIC

Analog IP is more difficult to design and optimize for a given process node compared to digital IP, so any automation for analog designers is always welcome. The engineers at SMIC in China have customers that design analog IP and often they need to know how to optimize it for a specific process, so I watched a presentation by Josh Yang, Senior Director at SMIC recently about how they do this. SMIC has six fabs in China and they serve as a foundry with process nodes ranging from 0.35um down to 28nm, with 24nm and 14nm in development. Customers of SMIC design across many market segments, like: Power management, wire-line communication, image & display, MCU, smart card, wireless, mobile computing, memory, digital home and smart everything.

SMIC customer designs may be fabricated in more than one location, so using process monitoring is important to keep the process variations within an acceptable range allowing design centering to maximize yields. Shown below are sensitivity analysis results for a process parameter called Vtlin to uncover how it correlates to other parameters:

Process monitoring is both measured in silicon and modeled prior to silicon. Models are used to predict variations in: Idsat, Ioff, BVDS, Vtlin and Isub. Sensitivity analysis is then run on these models using a software tool from MunEDA called WiCkeDto determine which process parameters effect variation the most, and even predict model parameter variations in order to debug parametric yield issues in analog IP. The WiCkeD tool has also helped SMIC engineers to debug several functional issues with analog IP, like:

• 40nm 10bit SAR ADC ENOB issue
• 40nm 2.0G low jitter PLL maximum frequency issue
• 0.18um 12bit ADS with missing code issues in the GSM receiver
• 55nm 8bit ADC with distortion issues

Voltage Reference Optimization
One SMIC customer designed a voltage reference and regulator circuit, however two of the reference voltage values had higher variation in silicon than simulated with a 3 sigma range in monte carlo, so they wanted to know if it was a circuit issue in their IP or a process issue. SMIC engineers ran worst case analysis in WiCkeD and found good correlation to silicon measurements:

• VDD12 – 3 sigma minimum Vref=931.21m, 3 sigma maximum Vref=1.4681
• VDD15 – 3 sigma minimum Vref=1.1664, 3 sigma maximum Vref=1.8354

The tool flow at SMIC with WiCkeD for this type of circuit analysis follows the following steps:

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