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Secret Sauce for Successful Mixed-signal SoCs

Secret Sauce for Successful Mixed-signal SoCs
by admin on 03-31-2015 at 12:00 pm

For a design engineer engulfed in the daily rigorous routine of having to keep in sync with updates from various design team members as well the dictums of the design management team, the task of remaining up-to-date with the design information is very often daunting.

What design changes have been checked in this week? Is the verification team using the correct behavioral model of the analog IP? Is the layout for this design DRC/LVS clean? Looks like the schematic had some ECOs! What changed? Which rev. of the schematic was the layout created for? Is the physical implementation team using the latest pinout of the analog block? Did all teams use version X.X of the USB 3.0 IP?

Sound familiar? These are usually the questions that chip designers are plagued with these days in an increasingly complex and multi-site design environment. Most designers would prefer to focus on the design implementation — such as creating the design or perhaps managing the challenges of scalability and performance of analog/mixed-signal blocks at advanced process nodes — instead of dealing with the increased demands of system-on-chip (SoC) integration and working with various design teams (front-end digital, verification, physical integration, etc.). With design teams located either locally or at different locations across the globe, it becomes imperative for all teams to work in tandem to ensure smooth design handoffs at various stages of the design flow.

To ensure a cohesive work environment for designers, one which enables them to focus primarily on the design creation and implementation, while subtly handling the mundane aspects of managing the sanctity of huge amounts of design data, it becomes important to use a design data management system. Most mixed-signal design modules are co-designed, with design teams working closely and interfacing with each other, and keeping the different design views synchronized often represents a challenge. If the behavioral model, block abstract, layout, timing or power model is not synchronized, it can prolong the turnaround time or, in the worst-case scenario, force a silicon re-spin. Moreover, analog/digital integration at advanced process nodes requires close collaboration between the various teams.

Design teams ignore investing in a design management system at their own peril. To realize a successful mixed-signal tapeout, it has become important to invest in a design management platform that covers all types of designs – analog, digital, RF and mixed-signal – and one that is closely integrated with design tools from various EDA vendors. While some teams have invested in software-based data management systems, with additional layers built on top to adapt to mixed-signal designs, the reality is that they neither meet the rigorous demands of complex mixed-signal design flows nor provide optimal performance. The result is that the designer often has to spend considerable time manually managing the tool and the design data.

Figure-1: Stability of a mixed-design flow with and without a design management platform

The power and size of mixed-signal SoCs are quickly expanding to new levels of integration in order to accommodate highly demanding features in consumer, automotive, industrial, medical and bio-tech applications. This has led to new revolutions in various fields, such as bio-tech. Take the case of DNA sequencing using mixed-signal SoCs as an example. Genia Technologies, acquired by Roche Molecular Systems in June 2014, recently provided a detailed view of its SoC device for DNA sequencing at CDN LIVE in Silicon Valley. The life sciences chipmaker is developing a faster and more cost-effective way of sequencing DNA chains.

For a bio-tech novice like me, who has no clue about the ramifications of having a fast and an affordable means of DNA sequencing, this was quite an eye opener. DNA sequencing provides the ability to assess individuals’ genetic profiles over their lifetime. What this implies is that hospitals and medical clinics can monitor or screen for future diseases efficiently and cost-effectively to provide personalized health care. Since the variation in genes can make people respond differently to the same drugs, doctors now have a means to decide which drugs to prescribe.

The traditional methods of DNA sequencing have been very expensive and time consuming. Genia Technologies is aiming to create a device that can reduce the cost of the sequencing to a few hundred dollars as opposed to a few thousands today. Their SoC-based solution bypasses specialized, expensive optical sensors and instead uses mixed-signal semiconductor chip with a number of sensors. Genia Technologies is aiming to make the chips as inexpensive as the ones found in mobile phones, tablets and other consumer electronic products.

Genia’s NanoTag sequencing technique, developed in collaboration with Columbia University and Harvard University, uses a single DNA strand, which is then processed using tiny bioengineered nanopores. The chip reads the DNA sequence electronically with the help of a number of sensors. According to Hui Tian, vice president of Genia Technologies, electronic reading of single DNA strands requires less “informatics horsepower” to reconstruct a sequence accurately. Each sensor generates kilobytes of data per base and each bio-machine runs at a few bases per second. Each human genome sequencing requires nearly 180GB of data. What was equally interesting is that for the SoC to work as desired, once the SoC was taped out, it was sent to another foundry to form mini-wells and biocompatible electrodes on top of the wafer.

Figure-2: Genia’s technology – Nanopore sequencing

Genia claims that its SoC-based solution, developed at the cross-section of NanoTags and CMOS IC technology, brings the crucial advantage of single molecule capability coupled with semiconductor scalability. But how does Genia Technologies manage the complexity of building such a powerful and complex SoC device?

Genia’s Tian says that his company uses the SOS data and IP management system from ClioSoft Inc., which is tightly integrated with Cadence Virtuoso® technology to ensure collaboration and better design handoff between different design teams. Tian further elaborated on the design flow adopted to develop the analog part of Genia’s SoC design using Cadence design tools and ClioSoft’s SOS design data management to create a platform for sequencing single DNA molecules.

As teams continue to grow across multiple sites and regions, it is becoming necessary to have a collaborative solution for engineers and managers to manage design data, track project activities and deliver IP products in a timely, secure and efficient manner. This avoids design and tapeout delays in their SoC projects. While design data management is not a magic elixir that resolves all SoC delays, it mitigates the risk significantly and provides a path for greater designer productivity and design flow efficiency.

Also Read: Data Management: Bridging Digital and Analog Domains in RF Designs

Ranjit Adhikary is director of marketing at ClioSoft Inc. He has over twenty years of experience and has worked in companies such as Cadence Designs Systems, Magma Designs and Atrenta.