Lately I was studying about new innovations in memory world such as ReRAM and Memristor. As DRAM (although it has become a commodity) has found its extensive use in mobile, PC, tablet and so on, that was an inclination too to know more about. While reviewing Cadence’s offering in memory subsystems, I came across this whitepaperwhich provides a comprehensive description about some of the existing and some of the upcoming (in production) DRAM interfaces along with their Pros & Cons.
Obviously, due to price pressure, DRAM business is a volume game and there is not much scope of differentiation. However, amid increasing SoC size, architecture and complexity, and more importantly mobile market driving DRAM business, it’s worth paying attention to the important demand of increased bandwidth, operating frequency and low power consumption. In view of these demands, different architectures of DRAM interfaces are emerging. Let’s take a brief look at these here, but one must see the whitepaper to know more about the actual details and also the references to those such as JEDECand HMC.
LPDDR3 (Low-Power Double Data Rate 3) – This interface suits well for mobile devices which require high memory density and performance and low power consumption. This also has lower I/O capacitance which helps in achieving increased bandwidth and operating frequency.
LPDDR4 – This is the latest standard from JEDEC, optimized for next generation mobile devices. This will provide double the bandwidth of LPDDR3 at similar power and area. It has lower page size, multiple channels and reduced command/address bus pin count. This will be in mass production in 2014.
[Wide I/O 2 Architecture]
Wide I/O 2 – This is again from JEDEC, expected to reach mass production in 2015. This supports 3D-IC packaging for PC and server applications and can be used for high-end mobile applications. It covers high-bandwidth 2.5D silicon interposer and 3D stacked die packaging for memory devices. In this architecture, designers can use EDA tools to take advantage of redundancy at the logic level to minimize device failures. Cadence Encounter Digital Implementation allows designers to route multiple redistribution layers (RDL) into a microbump or to use combination bumps. If one bump falls, the remaining bumps can carry on normal operations.
In 2.5D staking, cooling is not much of a problem. However, in 3D staking heat dissipation from the middle of the stack could become a problem and hence needs careful thermal planning.
HMC (Hybrid Memory Cube) – This is being developed by Hybrid Memory Cube Consortium and supported by many semiconductor and technology companies. It combines high-speed logic process technology with a stack of TSV (Through-Silicon-Via) bonded memory die. This architecture allows more DRAM I/O pins and hence provides the highest bandwidth among all architectures (as high as 400G). In comparison to LPDDR3, a single HMC can provide 15X higher performance and consume 70% less energy per bit. However, the cost of this technology is also high.
HBM (High Bandwidth Memory) – This is an emerging standard for graphics, defined by JEDEC (JEDEC’s HBM task force is now part of JC-42.3 sub-committee), expected to be published by late 2013. It’s expected to be in mass production in 2015. It’s stacked DRAM die using TSV technologies to support bandwidth from 128GB/s to 256GB/s.
So which memory standard works best for your design? There is no definitive answer. It really depends on the requirements of the application for power, performance and area. And not to forget, price to pay. For example, LPDDR4 should be good enough for budget mobile market, whereas computer graphics with high resolution may require HBM.
It will be worthwhile to look at the Cadence whitepaperwhich has detailed analysis of these architectures and the information about what Cadence provides in support of these architectures, such as memory controller and PHY IP. It also provides Cadence’s roadmap to offer support for upcoming DRAM architectures. Cadence also provides memory model verification IP to verify memory interfaces and ensure design correctness.