High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers

High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers
by admin on 08-04-2020 at 10:00 am

If you are designing high-performance computing and networking SoCs for hyperscale data centers, then you require IP that enables large amounts of data to travel at very fast rates. Whether the IP is for true long reach or very short-reach die-to-die connectivity in multi-chip modules (MCMs), you must consider several essential
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WEBINAR: High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers

WEBINAR: High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers
by Daniel Nenni on 06-30-2020 at 10:00 am

If you are designing high-performance computing and networking SoCs for hyperscale data centers, then you require IP that enables large amounts of data to travel at very fast rates.

Whether the IP is for true long reach or very short-reach die-to-die connectivity in multi-chip modules (MCMs), you must consider several essential… Read More


How to Solve the Business Gap in SEMI Industry?

How to Solve the Business Gap in SEMI Industry?
by Eric Esteve on 12-21-2015 at 4:00 pm

This white paper about Cadence innovative mixed-signal IP concept “Cadence Multi-Link PHY IP (SerDes, Analog Front-end, and DDR) to Design SoC Platform breaking the “Business Gap” on 14/16FFdescribe the problem, the emergence of a “business gap” linked with incredibly high development cost when targeting most advanced … Read More


Advances in DDR IP Solution for High-Performance SoCs

Advances in DDR IP Solution for High-Performance SoCs
by Pawan Fangaria on 12-02-2015 at 7:00 am

In this era of high-performance, low-power, and low-cost devices coming up at an unprecedented scale, the SoCs can never attain the ultimate in performance; always there is scope for improvement. Several methods including innovative technology, multi-processor architecture, memory, data traffic management for low latency,… Read More


Don’t Mess with SerDes!

Don’t Mess with SerDes!
by Eric Esteve on 12-01-2014 at 2:23 am

SerDes stands for Serializer/Deserializer, and SerDes is a serious piece of design, requiring an extremely experienced team of analog engineers (below 10 years’ experience, you’re still a quasi-beginner). Better to rely on an analog guru to draw the SerDes architecture and manage the team! Why does SerDes is becoming more and… Read More


USB 3.0 IP on FinFET may stop port pinching

USB 3.0 IP on FinFET may stop port pinching
by Don Dingee on 08-19-2014 at 5:00 pm

Sometimes a standard is a victim of its own success, at least for a while as the economics catch up to the technology. When a standard like USB 3.0 is announced, with a substantial performance increase over USB 2.0, some of the use cases come on board right away. Others, where vendors enjoy a decent ROI with good-enough performance,… Read More


High Quality PHY IPs Require Careful Management of Design Data and Processes

High Quality PHY IPs Require Careful Management of Design Data and Processes
by Pawan Fangaria on 01-29-2014 at 10:05 am

In last few years IP design has grown significantly compared to the rest of the semiconductor industry. There are newer IP start-ups opening across the world, particularly in India and China. Amid this rush, I wanted to understand the actual dynamics pushing this business and whether all of these IPs follow quality standards. … Read More


Emerging Trend – Choose DRAM as per Your Design Need

Emerging Trend – Choose DRAM as per Your Design Need
by Pawan Fangaria on 09-11-2013 at 7:00 pm

Lately I was studying about new innovations in memory world such as ReRAM and Memristor. As DRAM (although it has become a commodity) has found its extensive use in mobile, PC, tablet and so on, that was an inclination too to know more about. While reviewing Cadence’s offering in memory subsystems, I came across this whitepaperwhich… Read More


Should an IP vendor become a PHY IP Dealer?

Should an IP vendor become a PHY IP Dealer?
by Eric Esteve on 07-07-2013 at 3:20 am

This is not a theoretical question. Imagine that you are developing and selling digital IP, like Interface Controller, PCI Express or USB 2.0 or 3.0, or MIPI Camera Serial Interface (CSI) or Display Serial Interface (DSI). If you look at companies like Synopsys, they have built their success on the “Integrated Interface IP” concept.… Read More


Rare earth syndrome: PHY IP analogy

Rare earth syndrome: PHY IP analogy
by Eric Esteve on 04-03-2013 at 10:34 am

If you ask to IP vendors selling functions, PHY or Controller, supporting Interface based protocols which part is the master piece, the controller IP only vendors will answer: certainly my digital block, look how complex it has to be to support the transport and logical part of the protocol! Just think about the PCI Express gen-3Read More