Increasingly the challenge with SoCs, especially for mobile, is not getting the performance high enough but doing so in a power-efficient manner. Handheld devices running multiple apps need high-speed processors that consume extremely low levels of power both in operating and standby modes. In the server farm, the limit is often getting power into the datacenter and getting the heat out again, and so even in the highest performance part of the market, energy efficiency is paramount. In addition, electronic systems are now subject to regulatory and design requirements such as EMI emission guidelines and surviving ESD tests.
All of this, of course, in an environment where chip area remains important since it drives both cost and form-factor (important especially for mobile where the devices are physically small and so components need to be small too). But there is more to cost than chip area. For example minimizing the package cost and not using the minimal amount of decoupling capacitance.
Optimizing all these conflicting requirements simultaneously requires a more inclusive multi-physics approach, and not doing domain specific (the chip, the package, the board) design and analysis. This is what Apache call chip-package-system or CPS.
The biggest bang for the buck in terms of reducing power is to reduce the supply voltage. But supply voltages are now getting close the the threshold voltage of the transistors which means that the noise margin to keep everything functional shrinks. In addition, in standby mode, we need to control the amount of sub-threshold leakage. This all puts a lot of pressure on keeping the power supply clean all the way from the regulators, through the PCB in through the package and around the power grid on the chip. This is the power delivery network, or PDN. To ensure reliably power, the whole PDN needs to be optimized and validated together.
For high performance designs, thermal analysis is another important aspect of the design. For very high performance designs, such as servers, there may be heat sinks and fans that affect the overall cost of the design. For lower performance designs where the system is physically small, such as a smartphone, there are obviously no fans. But heat dissipation and the thermal analysis that goes along with it is a challenge. The transistors on the chip are affected by temperature and so it is not just a reliability issue but it can be a performance issue too. So integrated thermal analysis of chip, package and system becomes a necessary design step.
Apache has a good overview of all these issues in their white paper on Chip-Package-PCB Design Convergence. This is just one of the white papers that have been pulled together into a microsite that brings together all Apache’s material to do with CPS, including the CPS User Group. The Apache CPS micro-site is here.Share this post via: