Mixed Signal SOC verification Webinar

When looking at the time to design and verify an SoC we’ve known for many years now that the verification effort requires more time than the design process. So anything that will shorten the verification effort will have the biggest impact on keeping your project on schedule.

A second trend is the amount of Analog content in a mostly Digital SoC, which further complicates the verification process because analog IP is created at the transistor level with schematics and uses a SPICE netlist for simulation.

To better understand how you can improve your next mixed-signal SoC consider attending a webinarfrom Concept Engineering and EDA Direct on July 30th where they will present how their STARvision PRO tool is used in the verification process.

Webinar Includes

• Easily understand and integrate IP in your next design
• Generate clean schematics from cell library provided by foundries
• Quickly debug and traverse even the largest designs
• Mixed-language support for System Verilog, Verilog, VHDL, Spice, Spectre, DSPF, LVS
• Automatically generate schematics on the fly at RTL, Gate or Transistor level
• Automatic Logic Cone Extraction
• Clock Tree Analysis
• Identifies Clock Domains and Clock crossing signals
• Cross Referencing netlist to Schematics
• Understand the topology and function of the circuit without having schematics
• Verify connectivity especially for multi fanin and fanout nets
• ERC Checking: Floating input and output nets, heavy connected nets, etc.
• Debug power/ground connectivity issues
• Analyze results of LVS runs and use the automatically generated schematics from the extracted SPICE netlists with RC network
• Full chip netlist tracing (top level integration and block level)
• Full access to design db using Tcl scripts

Details

When: July 30, 2013

Time: 10AM to 11AM (PDT)

Where: Online Webinar

Register: Online Here

Further Reading

• Visual AMS Debug, an update at DAC
• IC Design for Implantable Devices Treating Epilepsy
• Transistor, Gate and RTL Debug Update at DAC
• IC Test Debug at Altera
• Visual Debugging at Altera on Billion-Transistor Chips
• Visually Debugging IC Designs for AMS and Mixed-Languages

Concept Engineering is a privately held company based in Freiburg, Germany, founded in 1990 to develop and market innovative schematic generation and viewing technology for use with logic synthesis, verification, circuit characterization, circuit optimization, test automation and physical design tools. The company′s customers are primarily EDA tool manufacturers (OEMs), in-house CAD tool developers and semiconductor companies. For more information see http://www.concept.de.

*lang: en_US