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PCI Express in Depth – Data Link Layer

PCI Express in Depth – Data Link Layer
by Luigi Filho on 09-06-2020 at 6:00 am

PCI Express in Depth Data Link Layer

In the last article, i wrote about the physical layer, now let’s take a look in the next layer the data link layer.

The Data Link Layer serves as the “gatekeeper” for each individual link within a PCI Express system. It ensures that the data being sent back and forth across the link is correct and received in the same order it

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How an Nvidia/ARM deal could create the dominant ecosystem for the next computer era

How an Nvidia/ARM deal could create the dominant ecosystem for the next computer era
by Michael Bruck on 09-04-2020 at 6:00 am

PC operating profits

Over the past few weeks, there have been numerous reports about Nvidia’s overtures to acquire Arm. The news has mostly been obsessed about the $31 billion that Arm’s current owner, Softbank, paid for Arm and whether Nvidia could pay such an eye-watering price to buy this asset. There is also pushback from Herman Hauser who was one… Read More


Cerebras and Analog Bits at TSMC OIP – Collaboration on the Largest and Most Powerful AI Chip in the World

Cerebras and Analog Bits at TSMC OIP – Collaboration on the Largest and Most Powerful AI Chip in the World
by Mike Gianfagna on 09-03-2020 at 6:00 am

Cerebras Wafer Scale Engine

This is another installment covering TSMC’s very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC’s vast ecosystem collaborates with each other and with TSMC. The topic at hand was full of superlatives, which isn’t surprising… Read More


Lip-Bu Hyperscaler Cast Kicks off CadenceLIVE

Lip-Bu Hyperscaler Cast Kicks off CadenceLIVE
by Bernard Murphy on 09-02-2020 at 6:00 am

Lip Bu min

Lip-Bu (Cadence CEO) sure knows how to draw a crowd. For the opening keynote in CadenceLIVE (Americas) this year, he reprised his data-centric revolution pitch, followed by a talk from a VP at AWS on bending the curve in chip development. And that was followed by a talk by a Facebook director of strategy and technology on aspects of… Read More


WEBINAR: Addressing Verification Challenges in the Development of Optimized SRAM Solutions with surecore and Mentor Solido

WEBINAR: Addressing Verification Challenges in the Development of Optimized SRAM Solutions with surecore and Mentor Solido
by Daniel Nenni on 09-01-2020 at 2:00 pm

surecore solido webinar graphic

After spending a significant amount of my career in the IP library business it was an easy transition to Solido Design. I spent 10+ years traveling the world with CEO Amit Gupta working with the foundries and their top customers. In fact, the top 40 semiconductor companies use Solido. IP companies are also big Solido users including… Read More


Creating Analog PLL IP for TSMC 5nm and 3nm

Creating Analog PLL IP for TSMC 5nm and 3nm
by Tom Simon on 09-01-2020 at 6:00 am

PLL Optimizations

TSMC’s Open Innovation Platform’s main objective is to create and promote partnership for producing chips. This year’s OIP event included a presentation on the joint efforts of Silicon Creations, Mentor, a Siemens business and TSMC to produce essential PLL IP for 5nm and 3nm designs. The relentless push for smaller geometries… Read More


Protocol in Depth – USB

Protocol in Depth – USB
by Luigi Filho on 08-30-2020 at 10:00 am

Protocol in Depth USB

The USB protocol is a very complex protocol, so there is no way i can explain every detail in a post, but i can let much more easy to understand what happens in a bit level.

There isn’t much good material for easy understand about USB, so i made some assumptions for make easier explain everything. In this post i’ll explain… Read More


Making Full Memory IP Robust During Design

Making Full Memory IP Robust During Design
by Daniel Payne on 08-28-2020 at 10:00 am

64Mb SRAM example, memory IP

Looking at a typical SoC design today it’s likely to contain a massive amount of memory IP, like: RAM, ROM, register files. Keeping memory close to the CPU makes sense for the lowest latency and highest performance metrics, but what about process variations affecting the memory operation? At the recent DAC conference held… Read More


CEO Interview: Charlie Janac of Arteris IP

CEO Interview: Charlie Janac of Arteris IP
by Daniel Nenni on 08-28-2020 at 6:00 am

charlie janac


Charlie Janac is president and CEO of Arteris IP where he is responsible for growing and establishing a strong global presence for the company that is pioneering the concept of NoC technology. Charlie’s career spans over 20 years and multiple industries including electronic design automation, semiconductor capital equipment,… Read More


A Historical Case for Precision – or How a Gun Made in a Dungeon Changed the World

A Historical Case for Precision – or How a Gun Made in a Dungeon Changed the World
by Lee Vick on 08-26-2020 at 10:00 am

Flintlock Mechanism Wikipedia

We take for granted today the staggering precision of modern technology. Cars, electronics, robots and medical equipment, all come off the factory floor composed of effortlessly interchangeable parts; but this was not always the case. In the late 18th century most things that required any kind of precision were made by hand, … Read More