Banner 1 800X100 (1) (1)
WP_Term Object
(
    [term_id] => 178
    [name] => IP
    [slug] => ip
    [term_group] => 0
    [term_taxonomy_id] => 178
    [taxonomy] => category
    [description] => Semiconductor Intellectual Property
    [parent] => 0
    [count] => 2056
    [filter] => raw
    [cat_ID] => 178
    [category_count] => 2056
    [category_description] => Semiconductor Intellectual Property
    [cat_name] => IP
    [category_nicename] => ip
    [category_parent] => 0
    [is_post] => 
)

WEBINAR: Design Adaptive eFPGA IP

WEBINAR: Design Adaptive eFPGA IP
by Daniel Nenni on 09-18-2020 at 10:00 am

Menta Adaptive Design eFPGA Webinar 1

Since the start of PROMS, PLDs and FPGAs we have learned the importance of programmability in modern semiconductor design. Today we have eFPGAs for “design adaptive” embedded programmability and that is what this webinar is all about.

Several key points are discussed starting with the Law of Accelerating Returns as it applies… Read More


Parallel-Based PHY IP for Die-to-Die Connectivity

Parallel-Based PHY IP for Die-to-Die Connectivity
by Mike Gianfagna on 09-17-2020 at 10:00 am

Two converging trends for die to die connectivity in MCMs 1

 

Synopsys has released a Technical Bulletin entitled “Parallel-Based PHY IP for Die-to-Die Connectivity”. The piece is authored by Manuel Mota, senior product marketing manager, staff at Synopsys. Manuel has worked at Synopsys for 11 years in the IP area. Prior to that, he worked at MIPS Technologies, Chipidea (acquired… Read More


AI in Korea. Low-Key PR, Active Development

AI in Korea. Low-Key PR, Active Development
by Bernard Murphy on 09-15-2020 at 6:00 am

korea ai min

Based on press coverage and technical paper volume, you could be forgiven for thinking that Korea had decided to take a pass on AI mania, or maybe just to dabble a little here and there to stay abreast of trends. But you’d be wrong. Korea is very active in AI; they don’t feel a need to trumpet what they’re doing from the rooftops. If you … Read More


Analog Bits at TSMC OIP – A Complete On-Die Clock Subsystem for PCIe Gen 5

Analog Bits at TSMC OIP – A Complete On-Die Clock Subsystem for PCIe Gen 5
by Mike Gianfagna on 09-09-2020 at 10:00 am

Design Integration of Complete On die Clock Subsystem for PCIe Gen 5

This is another installment covering TSMC’s very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC’s vast ecosystem collaborates with each other and with TSMC.  The talk covered here focuses on a complete on-die clock … Read More


Blue Cheetah Technology Catalyzes Chiplet Ecosystem

Blue Cheetah Technology Catalyzes Chiplet Ecosystem
by Tom Simon on 09-09-2020 at 6:00 am

Blue Cheetah Ecosystem

There are many reasons today for dividing up large monolithic SoCs into chiplets that are connected together inside a single package. Let’s look at just some of these reasons. Many SoCs share a common processing core with application specific interfaces and specialized processing engines. Using chiplets would mean that it is… Read More


Combo Wireless. I Want it All, I Want it Now

Combo Wireless. I Want it All, I Want it Now
by Bernard Murphy on 09-08-2020 at 6:00 am

Mixed wireless

When we think of wireless it is natural to wonder “which one – cellular, Wi-Fi, BLE?” Our phones support everything but those are pricey devices. What if we wanted the same combo wireless option in a low-cost IoT device, maybe something that only need to send a small amount of data periodically? Logistics applications are a good example.… Read More


Dolphin Design – Delivering High-Performance Audio Processing with TSMC’s 22ULL Process

Dolphin Design – Delivering High-Performance Audio Processing with TSMC’s 22ULL Process
by Mike Gianfagna on 09-07-2020 at 10:00 am

Dolphin Design – Delivering High Performance Audio Processing with TSMCs 22ULL Process

TSMC held their very popular Open Innovation Platform event (OIP) on August 25. The event was virtual of course and was packed with great presentations from TSMC’s vast ecosystem. One very interesting and relevant presentation was from Dolphin Design, discussing the delivery of high-performance audio processing using TSMC’s… Read More


In-Chip Monitoring Helps Manage Data Center Power

In-Chip Monitoring Helps Manage Data Center Power
by Tom Simon on 09-07-2020 at 6:00 am

in-chip sensing

Designers spend plenty of time analyzing the effects of process, voltage and temperature. But everyone knows it’s not enough to simply stop there. Operating environments are tough and have lots of limitations, especially when it comes to power consumption and thermal issues. Thermal protection and even over-voltage protections… Read More


PCI Express in Depth – Transaction Layer

PCI Express in Depth – Transaction Layer
by Luigi Filho on 09-06-2020 at 7:00 am

PCI Express in Depth Transaction Layer

In the last article i write about the Data Link Layer, in this article i’ll write about the Transaction Layer.

This layer’s primary responsibility is to create PCI Express request and completion transactions. It has both transmit functions for outgoing transactions, and receive functions for incoming transactions.… Read More


PCI Express in Depth – Data Link Layer

PCI Express in Depth – Data Link Layer
by Luigi Filho on 09-06-2020 at 6:00 am

PCI Express in Depth Data Link Layer

In the last article, i wrote about the physical layer, now let’s take a look in the next layer the data link layer.

The Data Link Layer serves as the “gatekeeper” for each individual link within a PCI Express system. It ensures that the data being sent back and forth across the link is correct and received in the same order it

Read More