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12m FPGA prototyping sans partitioning

12m FPGA prototyping sans partitioning
by Don Dingee on 10-16-2012 at 9:30 pm

FPGA-based prototyping brings SoC designers the possibility of a high-fidelity model running at near real-world speeds – at least until the RTL design gets too big, when partitioning creeps into the process and starts affecting the hoped-for results.

The average ASIC or ASSP today is on the order of 8 to 10M gates, and that includes… Read More


Altera’s Real Impact with ARM based SOC FPGAs

Altera’s Real Impact with ARM based SOC FPGAs
by Ed McKernan on 10-16-2012 at 8:15 pm

At the annual Linley Processor Conference this past week a number of chip vendors proposed a raft of new networking solutions directed at solving today’s bandwidth issues. Perhaps the overall highlight of the conference was the recognition by Keynote Speaker Linley Gwennap of the shift that is taking place towards ARM based solutions.… Read More


Altera’s Use of Virtual Platforms

Altera’s Use of Virtual Platforms
by Paul McLellan on 10-11-2012 at 9:00 pm

Altera have been making use of Synopsys’s virtual platform technology to accelerate the time to volume by letting software development proceed in parallel with semiconductor development so that the software development does not need to wait until availability of hardware.

In the past, creating the virtual platform … Read More


The Middle is A Bad Place to Be if You’re a CPU Board

The Middle is A Bad Place to Be if You’re a CPU Board
by Don Dingee on 10-09-2012 at 10:45 pm

In a discussion with one of my PR network recently, I found myself thinking out loud that if the merchant SoC market is getting squeezed hard, that validates something I’ve been thinking – the merchant CPU board market is dying from the middle out.… Read More


Aldec-Altera DO-254

Aldec-Altera DO-254
by Daniel Nenni on 09-25-2012 at 9:58 pm

As described in DO-254, any inability to verify specific requirements by test on the device itself must be justified, and alternative means must be provided. Certification authorities favor verification by test for formal verification credits because of the simple fact that hardware flies not simulation models. RequirementsRead More


ASIC Prototyping with 4M to 96M Gates

ASIC Prototyping with 4M to 96M Gates
by Daniel Payne on 09-17-2012 at 9:30 am

I’ve used Aldec tools like their Verilog simulator (Riviera PRO) when teaching a class to engineers at Lattice Semi, so to get an update about the company I spoke with Dave Rinehart recently by phone. A big product announcement by Aldec today is for their ASIC prototyping system with a capacity range of 4 Million to 96 Million… Read More


A Brief History of FPGAs

A Brief History of FPGAs
by Daniel Nenni on 08-26-2012 at 7:30 pm

From the transistor to the integrated circuit to the ASIC, next comes programmable logic devices on the road to the mainstream fabless semiconductor industry. PLDS started in the early 1970’s from the likes of Motorola, Texas Instruments, and IBM but it wasn’t until Xilinx brought us the field programmable gate array (FPGA)… Read More


Virtual Platforms plus FPGA Prototyping, the Perfect Mix

Virtual Platforms plus FPGA Prototyping, the Perfect Mix
by Paul McLellan on 06-03-2012 at 8:59 pm

There are two main approaches to building a substructure on which to do software development and architectural analysis before a chip is ready: virtual platforms and FPGA prototyping.

Virtual platforms have the advantage that they are fairly quick to produce and can be created a long time before RTL design for the various blocks… Read More


AMS Programmable Prototype Platforms

AMS Programmable Prototype Platforms
by ahmed.shahein on 05-21-2012 at 10:25 am

AVNET released their 15[SUP]th[/SUP] Xfest this year, a couple of months ago. It was here in Germany last week. It was a well organized event, rich with invaluable technical information and full of decent smart engineers and managers. If you missed it this year register for the next event as soon as you can.

It was a very successful… Read More