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WIKI Multi FPGA Design Partitioning 800x100
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Zynq out of the box, in FPGA-based prototyping

Zynq out of the box, in FPGA-based prototyping
by Don Dingee on 12-10-2012 at 11:24 am

Roaming around the hall at ARM TechCon 2012 left me with eight things of note, but one of the larger ideas showing up everywhere is the Xilinx Zynq. Designers are enthralled with the idea of a dual-core ARM Cortex-A9 closely coupled with programmable logic.

One comment a Xilinx partner made to me recently is that Zynq is the solution designers have been looking for when they run up against a bottleneck in an SoC, and need hardware acceleration of a handful of particular functions in FPGA gates. I also see Zynq as the solution for the “last inch”, where an off-the-shelf processor core (in this case two) needs some specific piece of I/O which can fit nicely in an FPGA. Both of these uses illustrate the idea that designers are headed from board design to SoC design in many cases, pulling functions inside a programmable device that used to be added on a board.

Unleashing the Zynq on a design team opens up a world of creativity, but it also opens up the same can of complexity we’ve been talking about recently: how to perform hardware-software co-verification, on an actual device, at or near full speed. That is the purpose of the HES-7 FPGA-based prototyping platform, and the folks at Aldec have introduced their latest enhancement: ARM Cortex-A9 support with a Zynq-based daughterboard.

There are two distinct personalities to a Zynq: the ARM Cortex-A9 processing cores, and the onchip programmable logic. It is an SoC, meaning the ARM cores can be brought up without anything on the programmable logic side. This is considerably different from previous approaches Xilinx and other vendors have taken, where a small processing core was an adjunct to the FPGA.

To deal with more powerful devices like Zynq, the HES-7 has two Xilinx Virtex-7 FPGAs. The Zynq daughterboard design is physically partitioned across both Virtex-7 devices on the HES-7 motherboard. According to Bill Tomas, product engineer at Aldec, this allows prototyping designs with very high performance I/O such as quad Gigabit Ethernet ports while at the same time running both Cortex-A9 processing cores at up to 1 GHz.

What can be done with this type of configuration? Consider the idea of a vision system. When I recently spoke with Jeff Bier of the Embedded Vision Alliance, he described the vision problem in terms that are very familiar from the world of phased array radar. At the front end, there is a large amount of high-bandwidth data and the algorithms are relatively fixed – a good application for an FPGA. At the back end, once pre-processing has detected regions of interest, a general purpose processor sifts through the data with a variety of algorithms often based on what is going on in the scene.

Until now, that kind of compute power wasn’t available in a single device. Tomas echoed that idea in the range of applications Aldec sees for Zynq, combinations of parallel processing in programmable logic and serial processing in the processor cores. Besides the GigE interfaces, Aldec has also worked in Bluetooth, Wi-Fi, HDMI, audio, USB 2.0, and a range of memory interfaces to give the Zynq designer room to explore multimedia applications using the HES-7.

Want to learn more about Xilinx Zynq and its capabilities? For another perspective, watch this episode of The #50Bdev Hangout, where I talk with a product manager from Xilinx and other folks about the device.

One unique twist to this story: Aldec feels so strongly about the Xilinx Zynq capability and what it can do for designs, they’re giving the daughterboard to existing and new HES-7 dual-FPGA customers. In the context of what else the HES-7 does, designers are sure to welcome ARM Cortex-A9 support.


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