Every analog designer needs a foundry PDK (Process Design Kits) and EDA tools to design, layout and verify their AMS chip or IP. This week I had a chance to conduct an email interview with Taek-Soo Kim, VP of Technical Engineering at Dongbu HiTek in Korea. This specialty foundry supplies analog silicon worldwide.
Q: Tell me about your background and how long have you been at Dongbu HiTek?
A: I have been in the Semiconductor industry for 26years. My main experience is in EDA, developing tools, setting up design methodology during first 15 years. Then I was responsible for design services operation in ASIC biz. Now I have been with Dongbu HiTek for 4 years and main responsibility is all design infrastructure.
Q: How long have Dongbu HiTek and Tanner EDA been working together on PDKs?
Q: What was the deciding factor to make the PDK for the BD180LV process (instead of the Medium-High Voltage, Ultra-High Voltage or Analog CMOS)?
A: Main reason is that this process happened to be the one our customer selected to use.
Q: Can you mention your first Tanner EDA customers that are using this PDK?
A: Unfortunately, we cannot disclose the name of this customer.
Q: Can you mention the end-product or industry that the first customers are using this PDK for?
A: DC-DC converter
Q: What other PDKs do you create ?
A: Cadence, Mentor, Synopsys, SpringSoft, iPDK
Q: How would you compare the effort of creating the PDK for Tanner EDA versus other PDKs?
A: For the first project that was done on 0.35um node, Tanner EDA engineer needed to get used to Dongbu HiTek technology. So, there was many communication going back and forth, but as things progress, thing got better.
Q: What would be the next PDK project that you will work with Tanner EDA on?
A: Plan to work on 60V extension of 0.18um BCD process.
Q: What do you like most about working with Tanner EDA?
A: Since Tanner EDA is not a big company, they are very active and shows very quick response.
Q: At the 180nm node about how long do most customer designs take to go from concept to tape-out?
A: within 6 month
Q: How many silicon re-spins does it take on average for your customers to get silicon designs ready for volume production?
A: Different on case by case but, on the average approximately 1 year.
Q: What is your Analog technology roadmap?
Q: What is new between Dongbu HiTek and Tanner EDA?
A: We just announced a foundry-certified 0.18 micron Analog CMOS PDK.
Q: When did Dongbu HiTek first offer the 0.18 micron node for analog designers?
A: Back in June 2008.
Q: What is unique with the BD180LV process node?
A: It has many analog components to choose from and can operate above 5V. This process has bipolar transistors as well for high performance power devices.
Q: In my PDK for Tanner EDA tools what do I get?
A: You get schematic symbols, simulation models, layout rules and verification structures.
Users of Tanner EDA tools are all set to design and fab with Dongbu HiTek for their analog and mixed-signal IC designs. PDKs for the 0.18 micron node and 0.35 micron node are ready now and more nodes are planned.