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IC Place and Route for AMS Designs

IC Place and Route for AMS Designs
by Daniel Payne on 11-30-2014 at 7:00 am

High-capacity IC place and route (P&R) tools can cost $200K and more to own from the big three vendors (Cadence, Synopsys, Mentor), but what about IC designs that are primarily Big Analog and Little Digital? In the EDA world we often have multiple choices for tools, and there are affordable alternatives to place and route out there. To delve a bit into this space I watched an archived webinar titled, Tanner EDA’s New HiPer Place and Route Overview and Demo.Jeff Miller was the presenter, and we’ve met in person before several times at past DAC shows.

Related – Adding a Digital Block to an Analog Design

Place and route is just one piece of the bigger tool flow now offered by Tanner EDA, Aldecand Incentia for AMS designs as shown below:

This combination of EDA companies kind of reminds me of the alliance created by Viewlogic back in the 1990’s called the IC Power Team.

The P&R product name is called HiPer Place and Route, an option to the L-Edit layout editor. Typical designs for AMS P&R are around 50K gates and using mature process nodes (350 nm to 90 nm). File formats are de-facto standards like LEF and GDS for layout, Liberty for the cell timing data, and Verilog or VHDL as RTL input. An actual demo flow was presented:

  • Synthesis (DesignCraft by Incentia)
  • Placement (HiPer P&R)
  • Clock tree synthesis (HiPer P&R)
  • Clock routing (HiPer P&R)
  • Signal routing (HiPer P&R)
  • SDF extraction (HiPer PX)
  • Timing Verification (TimeCraft by Incentia)
  • DFT (TestCraft by Incentia)
  • ECOs
  • Physical Verification

Related – Affordable AMS EDA Tools at DAC

An 8 bit ADC (Analog Digital Converter) was the demo circuit, written in Verilog. Scripts were used for logic synthesis in the DesignCraft tool. For placement a rectangular region was defined and then the IOs were added, 10 rows were defined, LEF files read in, and the Verilog netlist imported. Actual placement took just a few seconds:

Clock buffering was skipped for this small design, filler cells were added for power and ground, power rails were added to the sides, and then routing was run using 3 layers:

Connectivity checks were run to confirm that no shorts or opens were detected, an then an SDF file was created from extracted interconnect for timing delays. TimeCraft was run using scripts and the output was a report on worst-case timing paths, since the timing requirements were all met there was no iteration required. The demo was simple, short and convincing.

Related – A New Digital Place and Route System


Q: What is the smallest geometry process that customers have used this IC design flow on?
We’ve had customer designs done at the 65 nm process node with our tool flow.

Q: What is the largest design that you’ve run this on?
Almost 200K gates have been used with this tool flow, although we see 50K as the more typical design size.

Q: How do I get an evaluation of this P&R tool?
Contact salesw@tanner.com to get started.


EDA companies like Tanner EDA, Aldec and Incentia have partnered to create a complete AMS design and verification flow. The new P&R tool has a capacity up to 200K gates, and works well for the Big A, Little D style of AMS designs. It was refreshing to see an EDA vendor actually run their tool live, instead of canned, because it produced results so quickly for the demo design. Give Tanner a call if you are doing AMS designs down to the 65 nm process node. View the complete archived webinar here, after a brief registration process.

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