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Adding a Digital Block to an Analog Design

Adding a Digital Block to an Analog Design
by Daniel Payne on 10-30-2014 at 7:00 am

My engineering background includes designing at the transistor-level, so I was drawn to attend a webinar today presented by Tanner EDAand Incentia about Adding a Digital Block to an Analog Design. Many of the 30,000 users of Tanner tools have been doing AMS designs, so adding logic synthesis and static timing analysis from Incentia makes sense to fill out the design flow.

Jeff Miller from Tanner EDA presented the overall AMS tool flow, including Incentia tools for big A, little D designs:

Steve Lin from Incentia talked about their digital design flow from RTL to gates with timing and power closure:

Logic synthesis is provided by the Incentia tool called DesignCraft, and it uses industry standard file formats like:

  • Verilog, VHDL
  • Synopsys .LIB, CCS Library
  • SDC for timing constraints
  • VCD, SAIF and FSDB files for switching activity
  • SDF – standard delay format
  • Tcl scripting

Incentia also supports a DFT methodology with their TestCraftDFT tool, then interface to ATPG tools from multiple vendors: Mentor, Synopsys and SynTest.

Related – Affordable AMS EDA Tools at DAC

Following logic synthesis the next step is Place and Route using the HiPer Place and Route tool from Tanner, typically handling designs up to 50K gates. Standard file formats are supported, like:

  • LEF, DEF
  • GDS
  • Liberty for cell timing
  • Verilog gate-level netlist

Placement, clock routing, and n-layer auto routing steps were reviewed, and the finished layout has SDF for use in timing analysis.

Related – A New Digital Place and Route System

For static timing analysis the tool from Incentia is called TimeCraft which accepts the SDF file from P&R. Signal Integrity (SI) issues are accounted for, along with IR drop. Multi mode, multi corner (MMMC) analysis is supported, allowing you to do timing analysis across a grid or LSF to reduce run times. The largest design run through TimeCraft has been a 100M instance tape-out.

At 65 nm and smaller geometries the on-chip variation (OCV) can start to produce overly-pessimistic timing analysis results. Location-based OCV (LOCV) can also be taken into account with the TimeCraft tool. With the LOCV approach you will have fewer timing violations, plus smaller worst-case negative slack, making timing closure happen quicker.

The Incentia tool called ECOCraft supports Engineering Change Orders (ECO) to fix setup or hold time violations after P&R. Leakage power values can be reduced by running the ECOCraft Power tool by optimizing the use of multi-Vt cells and cell-sizing.

A live demo was performed on a small block with an 8 bit ADC circuit including a Finite State Machine, written in Verilog. After logic synthesis was run using a script, then the layout editor was invoked and P&R setup and run (cell placement, clock buffer placement, de-coupling capacitors, filler cells, clock routing, signal routing, power routing).

An SDF file was created, then used in Static Timing Analysis (STA) with TimeCraft using another script. The results of STA look like:

I cannot remember the last time that an EDA vendor actually ran their tools live during a webinar, so kudos to Jeff at Tanner EDA for doing this today as proof of how fast this tool flow actually is. Tanner users will be pleased that they can complete their big A, little D designs using this AMS implementation flow with Incentia tools. The GUI and scripts looked easy to run and learn, so expect a quick ramp-up time.

The full 60 minute, archived webinar is available online after a short registration process.

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