Date: Thursday, June 16, 2022
Time: 11:00am – 12:00pm (PDT)
Overview
System designers face increasing challenges in meeting technical specifications and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continues to grow. Large pin counts of flipped and rotated ICs may… Read More
EMEAI Session
Date: Tuesday, June 14, 2022
Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST
System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped
Date: Tuesday, June 14, 2022
Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST
System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped and rotated
Last week, Cadence hosted its annual CadenceLIVE Americas 2021 conference. Four keynotes and eighty-three different talks on various topics were presented. The talks were delivered by Cadence, its customers and partners.
One of the keynotes was from Partha Ranganathan, VP and Engineering Fellow from Google. His talk was titled,… Read More
After teams sweat the details of SoC and industrial design, they turn to printed circuit board designers for magic. Here are a pile of chips and passives, and a schematic for interconnecting them. This is how much physical space the board can occupy. Connectors have to be here, and here, and mounting holes there, and there. There … Read More
My engineering background includes designing at the transistor-level, so I was drawn to attend a webinar today presented by Tanner EDAand Incentia about Adding a Digital Block to an Analog Design. Many of the 30,000 users of Tanner tools have been doing AMS designs, so adding logic synthesis and static timing analysis from Incentia… Read More
The EDAC Emerging Companies Comittee (would that be the EDACECC?) is organizing a free panel session one evening at DVCon. It is Monday February 27th from 6pm to 8.30pm. I don’t yet have a room but it will be at the DoubleTree Hotel where DVCon is being held.
EDA companies often address hardware/software co-design from a hardware… Read More
