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Chips and pins and layers within

Chips and pins and layers within
by Don Dingee on 03-25-2015 at 3:00 pm

After teams sweat the details of SoC and industrial design, they turn to printed circuit board designers for magic. Here are a pile of chips and passives, and a schematic for interconnecting them. This is how much physical space the board can occupy. Connectors have to be here, and here, and mounting holes there, and there. There are a few constraints in power domains, signal routing, and thermal hotspots to worry about. From that point, skilled PCB layout artists create and cross check the layout, and the Gerber files go off to the board house for fabrication.

What usually happens next is the phone rings. It’s the purchasing agent mewling about how expensive these 12 or 16 layer boards are, especially with blind and buried vias. Discuss. The boards are too large for palletization, and the volumes too small or the risk too large to pre-order quantities. Cutting out layers is an EMI nightmare, and the routing is really congested in a few spots around these big BGAs as it is. We did the best we could, and it works, right?

If a PCB designer lives long enough, he or she acquires tribal knowledge in creating an acceptable balance between degree of difficulty, schedule, and cost. Respins draw the wrath of engineering managers quickly, but are rationalized as an unavoidable part of the cycle of learning around a new complex SoC. Advanced PCB layout tools with automated place and route and simulation capability have helped the cause.

What are we missing? Optimizing a system design implies tweaking parameters. In the traditional “over-the-wall” PCB design process, there really isn’t very much that can be tweaked. The chips are chosen, and their pinouts and packages selected based on chip-level cost and performance. The schematic is fixed, as are the footprint and mechanical constraints.

All that holds true when using merchant market ICs. One would hope the chip vendor did a reasonable job in selecting a package and pinout, and provided some layout hints in a reference design. They sell the same chip perhaps in several packages to a number of applications, and make choices and compromises for broader use. Inevitably, their optimum environment never seems to match your device design – and your PCB designer lives or dies with the results.

What’s that? Your team designs your own SoCs? Optimum now means something very different. In theory, if one could tweak a SoC pinout and package, the PCB layout could be simplified, maybe even layer-reduced. Beyond that, it might be cheaper to combine chips in a single package, such as a wireless interface or stacked memory, and then place that combination on a board, saving critical routing or space. If we had better tools to understand that before committing to a SoC package and PCB design ….

Co-designing SoCs, packages, and boards to achieve more cost-effective systems is the objective of the new Xpedition Package Integrator from Mentor Graphics. Getting out of spreadsheets and into virtual die models and early visualization breaks down the barriers between IC, package, and board design – and creates an opportunity for pathfinding that can lead to system cost reduction.

Data wins. Instead of just blithely picking a package option based on chip cost, a team can now run several scenarios to see which one produces a better PCB layout. Living with a bad SoC pinout leading to board layout congestion may not be necessary. Nuances of interposers and stacking techniques can be quickly visualized at a system level.

Xpedition Package Integrator has many features, with one of the biggest being multi-view connectivity management. Signals automatically map across design domains, in tabular or graphical modes, and are automatically re-sequenced as changes occur. User definable rules guide assignment and optimization of smart-pins. Library data is automatically generated and can be customized for company standards. Modeling using HyperLynx, Nimbic, and FloTHERM enable analysis and early exploration.

 The level of integration Mentor Graphics has achieved might seem to be just a logical progression in PCB layout tools, but it is really more than that.

This approach frees the tribal knowledge trapped in the respective heads of experts across an organization. The packaging expert is no longer passing pinout spreadsheets around, hoping everyone gets signal names right. The CAD library symbol expert is no longer working in a vacuum. The PCB layout artist is no longer forced to choose between really bad and not so good in making everything fit. The engineering manager has data from design tradeoffs made early. Signoff for manufacturing becomes easier. The purchasing agent has a better story with facts that maybe a bit more spent on a particular part resulted in a cost savings at the system level. Product marketers appreciate better margins, or more competitive pricing.

What I like about this announcement is how Mentor developed the tool. This was not a bunch of EDA geeks in a room thinking about how to sell more software by bundling features. This is about solving real problems at real SoC customers – like Intel, who co-authored a white paper presented at ISQED earlier this month with John Park of Mentor. There is another mobile SoC vendor Mentor asked me not to mention, who has been using pre-release versions of the tool for nearly two years.

Dave Wiens of Mentor called this approach an “EDA technology incubator”, where ideas and features are developed and tested on real-world designs before formal release, with Mentor and customer teams working together. Major SoC merchant vendors have seen the value, thinking through the problems encountered when using their chips in multiple form factors. I think we may see interchangeable packaging models from more vendors emerge as the tool gains traction.

Companies designing their own SoCs can now capture the same benefits. Xpedition Package Integrator is an amazing breakthrough, and I encourage anyone involved in SoC and PCB design to explore the details and reconsider the approach to cost optimization.

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