Transient Noise Analysis (TNA)

Tanner EDA Applications Engineers see a broad range of technical challenges that our users are trying to overcome. Here’s one worth sharing – it deals with transient noise analysis (TNA) for a comparator design. The customer is a producer of advanced flow measurement devices for application in medicine and research. The designer was trying to simulate (quantify) the jitter caused by the output noise of a comparator through its transition region. This signal goes into a buffer – and the buffer should also contribute some amount of jitter. Performing a noise simulation to assess the total onoise while biasing all devices in the transition region (the comparator being a very high-gain amplifier) resulted in very high total output noise.

The Designer was using LTSpice to run AC simulations with noise to calculate onoise and then divide it by the gain of the comparator to get equivalent inoise. The calculated inoise was then used to run a transient simulation. SPICE simulators include small-signal AC analysis that calculates the noise contributed by various devices as a function of frequency. This noise analysis applies to simple circuits that operate at a constant DC operating point.

To obtain better insight into the problem, we used the Tanner-AFS Transient Noise Analysis (TNA) to simulate the realistic noise with the customer’s data. We setup a test bench in S-Edit to run TNA with T-AFS. Working closely with the Designer, we measured maximum Peak-to-Peak Period Jitter and a maximum Peak-to-Peak Absolute Jitter. The transient noise analysis was first run without noise. Then it was run with a noise seed of 500 and a noise scale of 1. Results of the simulations were analyzed and compared in W-Edit to determine the effect of noise. To see the spread of Period Jitter, a set of simulations were conducted (each using different seeds); with statistical measurements performed using histograms in W-Edit. The results were utilized to inform the final design, supporting a successful tape-out.

Tanner EDA will exhibit at DAC 2013, June 2-4[SUP]th[/SUP], in booth 2442 and in the ARM Connected Community® (CC) Pavilion, #921. The entire analog and mixed-signal design suite will be demonstrated:

• Front-end design tools for schematic capture, analog SPICE and FastSPICE simulation, digital simulation, transient noise analysis, waveform analysis,
• Back-end tools, including analog layout, SDL, routing and layout accelerators as well as static timing and synthesis, and
• Physical verification, including DRC and LVS.

Visit www.tannereda.comto learn more. DAC demo sign-ups are HERE.

Tanner EDA provides a complete line of software solutionsthat drive innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs) and MEMS. Customersare creating breakthrough applications in areas such as power management, displays and imaging, automotive, consumer electronics, life sciences, and RF devices. A low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership (TCO). Capability and performance are matched by low support requirements and high support capability as well as an ecosystem of partners that bring advanced capabilities to A/MS designs.

Founded in 1988, Tanner EDA solutions deliver just the right mixture of features, functionality and usability. The company has shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries.

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