Circuit Simulator 2X/3X Faster than FastSPICE on Full Chip Simulation

Circuit Simulator 2X/3X Faster than FastSPICE on Full Chip Simulation
by Daniel Nenni on 11-11-2020 at 1:00 am

Webinar 2

Typical applications for SPICE simulators include analog, small and middle size digital and memory blocks, whereas FastSPICE simulators targets larger blocks or full chip simulations including memory circuits, SoCs. SPICE is very accurate but cannot handle large designs and simulation time can be extensive. While FastSPICE… Read More


Free Webinar on SPICE Simulation

Free Webinar on SPICE Simulation
by Tom Simon on 10-31-2020 at 10:00 am

SPICE Simulation

The world of SPICE simulators is one filled with compromises. Typically, it is possible to choose the highest accuracy and pay a performance and capacity penalty, or to choose high speed and capacity but give up accuracy in the process. Many semiconductor companies have been turning to Primarius Technologies to help escape these… Read More


Creating Analog PLL IP for TSMC 5nm and 3nm

Creating Analog PLL IP for TSMC 5nm and 3nm
by Tom Simon on 09-01-2020 at 6:00 am

PLL Optimizations

TSMC’s Open Innovation Platform’s main objective is to create and promote partnership for producing chips. This year’s OIP event included a presentation on the joint efforts of Silicon Creations, Mentor, a Siemens business and TSMC to produce essential PLL IP for 5nm and 3nm designs. The relentless push for smaller geometries… Read More


Webinar on TFT and FPD Design

Webinar on TFT and FPD Design
by Daniel Payne on 05-11-2017 at 12:00 pm

I knew that the acronym for TFT meant Thin Film Transistors, but I hadn’t heard that FPD stands for Flat Panel Detectors. It turns out the FPD are solid-state sensors used in x-ray applications, similar in operation to image sensors for digital photography and video. I’ll be attending and blogging about what I learn… Read More


How 16nm and 14nm FinFETs Require New SPICE Simulators

How 16nm and 14nm FinFETs Require New SPICE Simulators
by Daniel Payne on 02-07-2016 at 7:00 am

About 35 years ago the first commercial SPICE circuit simulators emerged and they were quickly put to work helping circuit designers predict the timing and power of 6um NMOS designs. Then we had to limit our circuit simulations to just hundreds of transistors and interconnect elements to fit into the RAM and complete simulation… Read More


AMS Verification and Regression Testing of SoC Designs

AMS Verification and Regression Testing of SoC Designs
by Daniel Payne on 03-25-2014 at 10:02 am

Digital verification engineers on SoC designs have adopted many techniques to help ensure first silicon success: using compiled simulators, constrained random test, simulation farms, SystemVerilog methodology, and self-checking testbenches. AMS verification has tended to be ad-hoc or sharply divided into separate analog… Read More


BDA Takes on FinFET-based Memories with AFS Mega

BDA Takes on FinFET-based Memories with AFS Mega
by Daniel Nenni on 05-29-2013 at 12:00 pm

Berkeley Design Automation today announced the first silicon-accurate circuit simulation for mega-scale arrays like memories and CMOS image sensors. If this tool lives up to its claims, it is going to be a big deal for FinFET-based circuits, Memory designers are rightly worried about having the accuracy necessary to include… Read More


Improving Design Practices for an Image Sensor IDM

Improving Design Practices for an Image Sensor IDM
by klujan on 05-07-2013 at 8:30 pm

With nearly twenty five years in business, Tanner EDA Application Engineers have seen a wide range of support requests. One consistent topic area is around design data management and design reuse. In one recent instance, our customer, an IDM who produces imaging sensors for infrared vision systems, called on Tanners AE team for… Read More


Hot Topic – CMOS Image Sensor Verification!

Hot Topic – CMOS Image Sensor Verification!
by Daniel Nenni on 04-29-2013 at 7:30 pm

Mobile applications require CMOS image sensor devices that have a low signal-to-noise ratio (SNR), low power, small area, high resolution, high dynamic range, and high frame rate. CMOS image sensor imaging performance is noise limited requiring accurate noise analysis on the pixel array electronics and column readout circuitry.… Read More