Designing a Wafer-Scale Image Sensor for use in X-Rays

At Intel we mused about designing wafer-scale integration (WSI) back in the 70’s however I just learned about how Dr.Renato Turchetta at the Science and Technology Facilities Council (STFC) designed a wafer-scale imaging sensor chip for X-Ray applications. I was also able to interview Dr. Turchetta to learn more about the challenges that they faced in creating this chip.

Here’s a photo of the 139.2 mm x 120 mm CMOS image sensor they designed that can be abutted 2×2 to create an effective array of 278.4 mm x 240 mm:

Just to remind you of how huge this image sensor is remember that a cigarette is only 100 mm in length, so just one of these sensors is larger in dimension than a cigarette. As a visual comparison consider the typical Smart Phone today with a camera, the sensor size is more like this:

The foundry selected for this CMOS image sensor was TowerJazz and they used a 180/350nm dual-gate process with 200 mm wafers. So you get one CMOS image sensor per wafer, hence the wafer-scale integration. STFC had to collaborate closely with both TowerJazz and Tanner EDA to get first silicon success on this project.

This chip is mostly analog design with a little bit of digital control logic.

Q: How long have you been at STFC?
A: Since 1999.

Q: What did you do before STFC?
A: I was an Assistant Professor at the University Louis Pasteur in Strasbourg, France.

Q: What kind of IC designs is your group responsible for?
Full custom CMOS Image Sensors. We design the entire sensor, including the pixel.

PimMS

• Event based time-stamping pixel sensor
• 5 kilopixel spatial resolution (100 kilopixel version in design)
• 50 ns timing resolution
• 12 bit time-stamp storage
• 4 registers per pixel for multiple event detection
• Programmable threshold and per-pixel trim
• Analogue readout for focusing and event size measurement

I-ImaS

• 1.5 D sensor
• Designed for X-ray Medical Adaptive Imaging
• 32 µm pixel pitch
• 512 x 32 active pixels in focal plane
• Internal Programmable Gain Amplifier
• On-chip Successive Approximation ADCs
• 14-bit digital readout
• 72 dB dynamic range
• 20 Mpixel/sec clock rate

PEAPS

• Flexible Region-of-Interest readout sensor
• Designed for an optical tweezer application
• 25 µm pixel pitch
• 520 x 520 pixels
• On-chip Successive Approximation ADCs
• 12-bit digital readout
• 150 frames per second at full frame
• Any shape or size of regions can be programmed

LAS

• 2 Megapixels, large area sensor
• Designed for high-dynamic range X-ray imaging
• 40 µm pixel pitch
• 1350 x 1350 active pixels in focal plane
• Analogue readout
• Region-of-Reset setting
• 140 dB dynamic range
• 20 frames per second

ACHILLES

• 16 Megapixel, large area sensor
• Designed for direct detection of electrons in a Transmission Electron Microscope
• 14 µm pixel pitch
• 4096 x 4096 pixels in focal plane, all active
• Sensor Size: 61mm x 63mm
• Analogue readout
• Radiation hard
• Region-of-Interest readout
• Pixel binning: x2 and x4 in both directions

Q: How many IC projects does your group complete each year?
A: Between 5 and 10

Q: What is the range of complexity on your projects?
A: Wide!
For example, for the pixel we have designs where we use simple 3T architectures or other designs with ‘smart’ pixels which have over 600 transistors. Also, the data coming out of the pixel might be kept in analogue form and multiplexed to some fast output amplifiers or converted into a digital value on the chip. We have designed a wide range of ADCs: column-parallel single ramp, Successive-approximation for the readout of multiple column. In other projects in my lab, we also designed pipeline ort flash ADC. Because of our customer requirements, we do not tend to have any on-chip image processing or complex digital controls.

Q: Tell me about the Wafer-Scale CMOS Imaging Technology.
A: It is becoming trendy! In CMOS manufacturing, the largest area that can be printed on a wafer is limited by the reticle size. This is far smaller than the wafer, as it is limited to 2-3 cm in each direction. So a technique called ‘stitching’ is used. During the years, stitching has becoming more widely spread among CMOS foundries, in some cases becoming part of the standard offering. We at STFC has been designing stitched sensors for several years and we already have several designs, including a 16Mpixel for transmission electron microscopy. This sensor is at the core of a camera which is sold by one of the leading electron microscope manufacturers (FEI). Our experience allowed us to design a sensor which occupies a full 200 mm wafer and this without any previous prototyping.

Q: What were some of the design challenges in this latest sensor?
A: Wafer-scale. Designing a wafer-scale sensor is not the same as taking a small design and just tile it over a larger area. Design style changes in order to make the sensor manufacturable and with high yield.
3-side buttable. In a standard image sensor, the row and column control blocks would be on orthogonal side of the sensor. Also it is normal practice to have power rings around the pixel array. To make it 3-side buttable, the power ring has to disappear and the row control block has to move to the same side as the column control block. We also had to find a clever way to integrate some logic into the array without disturbing the image quality.

Q: Do you have competitors for this latest sensor?
A: There are other wafer-scale sensor around, but we believe our sensor has advantages in terms of spatial resolution and speed. The pixel pitch is 50 um and the readout speed is 30 fps. They are both at the high-end of performance and other sensors are in similar numbers for one of the two parameters but not for both. We also feature lower noise than similar sensors. All of these features, speed, spatial resolution, noise, are important for our main target application, i.e. digital Tomosynthesis mammography.

Q: What IC design tools are you using?
A: Mainly transistor level from Tanner EDA:

• Tanner Tools Pro:

  • T-Spice Pro (schematic, SPICE simulation, waveform viewing)
  • L-Edit Pro (IC layout)
• HiPer Verify (DRC, LVS, extraction)

Q: Was first silicon a success, or did you require re-spins? If so, why?
A: It was a first silicon success. Why? I would day mainly because of our expertise in designing large-area sensor.

Q: Why did you choose Tanner EDA tools?
A: The Tanner tools have a good price to quality ratio.The complete set of Tanner EDA tools was extremely well suited for the design of this sensor with its complex analog architecture. This, in conjunction with the high yield of the TowerJazz CMOS Image Sensor process technology, was instrumental in achieving a first-right-time design with no prerequisite for any initial prototype design.

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