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Imec and Coventor Partner Up

Imec and Coventor Partner Up
by Paul McLellan on 10-28-2014 at 7:00 am

 Today imec and Coventor announced a joint development project for 10nm and 7nm process development. Imec, which is in Leuven Belgium, is a partner with pretty much all the semiconductor companies that are planning work at these advanced nodes. It mostly does pre-competitive research and development. This type of research is very expensive for any one semiconductor company to carry out so it makes sense to share the investment across the entire industry. It will be interesting to see whether the GlobalFoundries acquisition of IBM’s semiconductor business changes the landscape since historically IBM has done a lot of research themselves, and those researchers now work for GF. Imec is a big operation with a staff of over 2000 people, including 670 industrial residents and guest researchers.

To adopt the 7nm node, the industry needs to select the optimal layout, as well as optimize process step performance and control methodology. Using Coventor’s SEMulator3D platform, engineers from imec and Coventor are working together to reduce silicon learning cycles and development costs by down selecting the options for development of next-generation manufacturing technologies. The SEMulator3D platform is an integrated set of modeling tools with enhanced visibility, accuracy and performance that enables engineers to interactively model and simulate a wide range of manufacturing effects in software before committing to expensive test chips.

At imec, process and integration experts have connected imec’s own optical lithography simulations with Coventor’s SEMulator3D virtual fabrication platform to explore FinFET scaling to the 7nm node and to compare the process window marginalities in several dense SRAM designs using Spacer Assisted Quadruple Patterning and either multiple immersion or EUV patterning cut/keep solutions. Moreover, a Spacer-Assisted Quad Patterning scheme for 7nm dense interconnect was devised using SEMulator3D, and process window marginalities for an immersion based multiple block patterning solution were analyzed.

Additional collaboration will focus on the predictive modeling of Directed Self-Assembly for advanced patterning. This is one of the great hopes “lithography in a bottle” for creating patterns at these very advanced nodes without requiring uneconomic numbers of process steps and assuming that EUV doesn’t come on line in time for 7nm (if it ever does).

Obviously at one level this provides imec the capability to do virtual fabrication using SEMulator3D but the tool itself is not static and needs to keep adding capabilities for 10nm and 7nm as development of these process nodes proceeds. As David Fried, Coventor’s CTO, said:Imec is the premier semiconductor research center, and this collaboration allows us to synchronize our modeling roadmap with one of the industry’s most advanced process roadmaps, as well as to speed the development of their 10nm and 7nm technology. Working together with imec on novel integration schemes, designing SEMulator3D-specific structures for imec’s testsites, and then calibrating advanced models to imec’s wafer processing is an extremely effective and valuable way for Coventor to optimize our virtual fabrication platform for emerging market requirements.

See also Imec’s Process Secret Decoder Ringand What Comes After FinFET?

More information on SEMulator3D is here.

More articles by Paul McLellan…

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