New Release of Semulator3D at #semiconwest

One of Coventor’s flagship products is SEMulator3D, and at Semicon West they announced a new version, 2014.100.

SEMulator3D is a powerful 3D semiconductor and MEMS process modeling platform. It uses highly efficient physics-driven voxel modeling technology. It models the physical effects of process steps, which is where all the current challenges are.

Combining the two-dimensional design layout with the process description gives it the capability to model the process flows and determine what will be manufactured with that combination of layout and process. The basic idea, as with all modeling, is to enable experiments to be done quickly and efficiently. Since the alternative is to actually build chips and then take measurements, which is millions of dollars of investment and months of delay, the virtual fabrication route is especially attractive. This is especially important in the early stages of process development since it can drastically shorten the whole development and ramp to volume roadmap.

Customers using the product include IDT, Infineon, IBM, Cavendish Kinetics and many others (who are being shy about going public). And talking about it in public at a presentation I attended at Semicon West was GlobalFoundries, who I didn’t even know were a customer (I’ll cover this in more detail in another blog once I get the slideset). They are also in a formal development program at imec for 7nm (which I will cover in a later blog).

The new release has major improvements on the modeling of etch. There are also improvements in accuracy for modeling deposition and CMP (chemical-mechanical polishing), which require analysis of planarization.

The biggest feature of the release is a new visibility-limited deposition model. This model dramatically improves the predictive accuracy for directional depositions, like Physical Vapor Deposition (PVD) and other plasma enhanced deposition processes. The key features of the visibility-limited deposition model are the “Source Sigma”, reflecting the directional distribution of the process, and the “Isotropic Ratio”, reflecting the non-visibility-limited component of the deposition process. This model enables a large variety of processes, with a wide range of results. As semiconductors get more vertical (FinFETs, TSVs, DRAM, MEMS etc) this is increasingly important.

The diagram above shows the same piece of a design modeled with various values for the source sigma and the isotropic ratio. You can see the difference from very directional deposition in the top row to much more conformal in the bottom row.

The new release also contains two modules addressing planarity. One addresses spin-on processes. These are meant to produce a perfectly planar surface but in fact some aspects of the underlying topology show through, how much depends on the thickness of the material being spun-on and its properties. It can even handle cases where the deposition is thinner than the features in the underlying topography, which can result in exposed structures.

Another module improves handling of CMP, predicting dishing and overpolish behavior in the presence of very non-planar underlying topography. I still find it amazing that CMP actually works, after all it is pretty much grinding the wafer, without wrecking what is on the wafer and without completely contaminating everything.

In summary, here are the new features in this release and the prior main April release:

• Modeling Performance Enhancements
• Selective Conformal (Basic) Etch now Multi-Threaded
• Multi-Etch speed enhancement
• Layout-Aware Rebuild
• Improves modeling performance response to design changes
• New GUI for the tool’s Expeditor feature
• Makes complex multi-dimensional DOEs easier to setup and execute
• Crystal Etch moved into the tool’s Process Editor
• Popular custom python, now in process library

More details on the new release are here.

More articles by Paul McLellan…