I spent all of last week at SEMICON West meeting with customers, potential customers, partners and various industry analysts and experts. I was involved in many interesting discussions over the course of the week and I thought I would share some of the more interesting observations:
Alternate Fin Materials Pushed Out
I have for some time been expecting that Intel would introduce Germanium (Ge) fins for PMOS at 14nm. Furthermore I had seen an announcement from TSMC that they would be introducing Ge fins at 10nm. My view was Intel would be the first adopter for Ge fins at 14nm and then the usage would become more widespread at 10nm. I furthermore expected we might see Indium Gallium Arsenide (InGaAs) fins for NMOS first use at 10nm and wide spread use at 7nm. What I am now hearing is that Intel has abandoned Ge fins for 14nm and TSMC has pushed them out to 7nm. It looks like adoption of Ge has been pushed out one node industry wide and presumably InGaAs will also be pushed out at least one node. Furthermore, what I am hearing is that Intel’s 14nm process is now a shrink of the 22nm process with no new technology introductions. I am also hearing Intel is still struggling with 14nm yields but they are ramping up anyway and working on yield as they go. Running volume can be a very effective way to make rapid progress on yield if you can afford the scrap.
450mm Still Delayed
After SPIE earlier this year I reported that 450mm was delayed until after 2020. Everything I heard at Semicon was consistent with this. My sense is that Intel and TSMC in particular have both backed off on their timing.
The continued delays in EUV are making insertion at 10nm less and less likely. Insertion at 7nm will either require a high NA tool or multi-patterning. Higher NA has a whole set of problems of its own to add to the current problem list. Meanwhile companies continue to cost reduce and prefect multi patterning.
28nm A Long Lived Node?
There have been a number of comments in the media about 28nm being a long lived node. I would just like to point out that all foundry nodes tend to be long lived. You can still get 500nm, 350nm, 250nm, 180nm, 130nm, 90nm, 65nm and 40nm nodes from TSMC, UMC and many others. In fact it wasn’t that long ago that I was hearing that 65nm was still the sweet spot for most designs, it might still be true. I think the real point people are trying to make is that 28nm will continue at higher than normal levels longer than normal because of a perceived lack of value at 20nm and below. I will discuss this more in the next two sections.
20nm Is Ramping at TSMC
Morris Chang has stated he expects 20nm to be the fasting ramping node in TSMC history. There are reports coming out that Qualcomm and Apple both have 20nm designs running at TSMC (Chipworks just announced an analysis of a 20nm Qualcomm part presumably purchased on the open market). It is pretty clear 20nm is going to be a big node at TSMC, I think the more interesting question is will 20nm take off anywhere else.
Scaling and cost
There have been a number of reports that cost reductions will end at 28nm and that at 20nm and 14nm cost per transistor will rise. Historically each new node has resulted in an increase in wafer cost but at the same time an even greater rise in transistor density has yielded a cost per transistor reduction. I had been planning to write an article on this and I still might, but I thought I would share some observations here.
At 20nm extensive multi-pattering is required driving up wafer cost more than “normal” versus the 28nm node, however, TSMC is reporting a 2X increase in transistor density for 20nm versus 28nm. 20nm wafer costs are not 2x 28nm wafer costs and cost per transistor should therefore go down although less than “normal” and I am in fact hearing that early adopters at TSMC are seeing reductions in cost per transistor.
This brings us to 14nm (or 16nm as TSMC calls it). 14nm is a very interesting node for several reasons. First of all it is the first FinFET node for most logic producers. Secondly, the major foundries have all decided to use the same backend for 14nm that they used for 20nm suggesting little or no increase in transistor density will result. There have been some projections of major increases in wafer cost at 14nm due to “FinFET and Multi-pattering”. Since most logic multi-pattering is in the backend and the backend isn’t shrinking I wouldn’t expect multi-pattering to drive a lot of additional cost versus 20nm. Also, FinFETs actually have simpler processes than bulk planar (less mask layers although some steps are very difficult) so I am not expecting an unusually large cost per wafer increase for 14nm versus 20nm. In terms of transistor density I am hearing there will be about a 5% to 10% improvement. The net result is I would expect cost per transistor to be relatively flat to slightly up at 14nm. What I am hearing is cost per transistor will actually go down, but only slightly.
At 10nm all the foundries are expected to do a full shrink. 10nm will require more complex multi-pattering schemes and I expect that the density improvement will result in a reduction in cost per transistor, although likely smaller than the “normal” trend.
200mm Growing Again
SEMI presented a very interesting data point that 200mm wafer volumes have gone up this year. Typically at this point in the life cycle of an older wafer size it would be in a slow steady decline and yet 200mm has grown recently. On top of this, presentations discussing “The Internet Of Things” all seem to include a discussion of all the additional 200mm fabs that will be needed to make the sensors. 300mm represents the majority of silicon wafer area run by the semiconductor industry today and is rapidly growing, 150mm and smaller wafer sizes are all declining but it looks like 200mm will also see some growth for at least the next few years. It will be interesting to see how this all plays out if 450mm is ever introduced. 450mm could result in a lot of low cost 300mm surplus hitting the market that might drive applications to jump from 200mm and smaller wafer sizes to 300mm. Low cost – used 300mm equipment and fabs have already led to the TI 300mm analog Fab and Infineon 300mm discrete fab.
There was a very interesting tech spot on 3D NAND run by Mike Corbett of Linx Consulting. Samsung presented on the market, Applied Materials on Deposition Challenges, Tokyo Electron on Etching Challenges and Mark Thirsk of Linx on materials and cost. 3D NAND appears positioned to provide a future scaling path for NAND with much better performance and eventually better cost. To-date 3D NAND is going into high-end applications (less cost sensitive) but with the introduction of a 32 layer devices later this year wider usage is expected. During the question and answer part of the session one person commented that the 3D cell sizes are a lot bigger than people realize. If you do the math he is correct, I get something like 26F2 as the effective cell size based on the size of the arrays. When you take into account 24 layers and 2 bits per cell, the area per bit is larger than current 16nm 2D NAND. However, when you get to 32 layers the area per bit is smaller and additional layers only increase the lead. 3D NAND continues Moore’s law and scaling by going into the third dimension. This is a technology to watch and it will be interesting to see if analogous solutions can be developed for DRAM and even logic.
The Shrinking Show Floor
Several years ago I had a booth at SEMICON West but I didn’t find the cost benefit trade-offs to be favorable. The last couple of years I have foregone a booth and just attended the show setting up meetings to take advantage of so many people I wanted to meet with all being in the same place at the same time. Walking the show floor this year it struck me as smaller than in the past. I have the impression that more and more companies are forgoing a booth on the show floor for off-site meeting space in surrounding hotels. If this is in fact an accurate view of what is happening this strikes me as a bad trend for SEMI and the show since they presumably get no revenue from off-site meetings.