The most interesting part of the semiconductor market for me has always been the Custom Chip sector – the FPGA, ASIC and SoC companies where I have spent my entire career. These three segments provide an excellent barometer of the overall state of financial health and technological innovation for the entire High Tech industry, from chips to systems to software.
All semiconductor markets – communications, computing, consumer, mobile, automotive, industrial, scientific, medical and defense/aerospace – use personalizable solutions from one or more of the above mentioned Custom Chip segments. Any combination of high growth, high complexity, high software content and short system product life cycles drives the need for customizable chip technology in some form.
The operational requirements of systems houses for custom logic offerings include rapid TTM, ease of use (both in terms of degrees of freedom in personalization and robust tools support) and low risk (both during and after the system design phase.) The combined technical requirements for customizable solutions, though, make it very tough to meet these operational constraints. The technical ‘pieces of the puzzle’ are represented by the diagram below.
The more of these requirements that are covered, as well as the depth of coverage, determines the value proposition of a given custom chip firm. How do each of the custom logic segments stack up to these prerequisites?
For maximum flexibility and 3P (price, performance and power)optimization in hardware, the ASIC solution cannot be bested. ASIC companies provide all the hardware components a system house needs in a custom chip –standard cell & I/O libraries, embedded memory and blocks for higher functionality or standard protocols (either directly or thru third parties) –and wraps them up in tools suites, model abstractions and methodology flows so that a system design team can paint on an open canvas of silicon as it sees fit.
The segment’s weaknesses, nonetheless, are just as glaring as its strengths are compelling. Low unit prices are more than countered by NRE costs,manpower expenses and painfully long design cycles. The other (and arguably more important) half of complex chip design – the software aspect – is almost entirely ignored by ASIC houses, with the exception of providing minimal API, driver and firmware support for certain embedded standard cores.
The worst flaw in the ASIC model is its total lack of flexibility once a design is captured in GDSII format. Further alterations are painful and time-consuming, while bugs and flaws discovered after product release can waste tens of $M’s in costs and 12-18 months of effort.
Programmable Logic companies live and die by their embrace of complete flexibility thru logic emulation. They have dominated the bottom right of the technical requirements puzzle for over 30 years.
Emulation has its drawbacks, as programmable logic has been a notoriously poor solution with respect to the three P’s (though Lattice of late has provided a notable exception with its iCE product lines.) The segment’s participants have tried hard to ameliorate this deficiency thru embedding hardwired CPUs, SERDES, PLL/DLL and other standards-based blocks. PLD firms have also made major, sustained efforts to address all of the other puzzle pieces. This infusion of value has allowed FPGA companies to largely preserve their historic 60% gross margins.
Yet further technical progress and revenue growth is blocked by the very core of the FPGA value proposition – its programmability. For decades,the leading vendors have turned bit-level configurability into an obsessive cult that permeates everything they do. Challenging this technology orthodoxy internally has long been heretical, and both technical & business progress have been largely hamstrung for the last decade as a consequence.
Though many chip companies fancy themselves to be System-on-Chip enterprises,few genuinely have the technical expertise to back that claim. Those that do maintain incredibly rich embedded IP portfolios of both hardware and software.Their solutions consist of chip designs with a smorgasbord of processing elements, accelerators, analog & mixed signal modules and standard blocks along with a co-developed software stack including firmware, OS, middleware and even applications code. Personalization of the solution to a system OEM’s application is accomplished thru software, and a toolchain supporting the SoC’s embedded processors is provided as part of the software distribution.
The founders of companies like Broadcom and Qualcomm had an abundance of both courage and vision, pursuing a level of system expertise that conventional standard product firms of the time thought were simply beyond the reach of chip houses. As a result of their efforts, an amazing amount of value was passed down from systems houses to these SoC firms – a value which is reflected in their balance sheets.
The SoC companies have to a great extent captured the strengths of their ASIC and FPGA competitors while having none of their faults. There can be no question that the SoC segment is the king of the hill in the customizable chip market. Yet a set of circumstances has arisen which will shake the foundations of the entire sector.
When one looks back at the last two years of market performance for the semiconductor industry, it is evident that memory prices – DRAM and, to some extent, Flash – have driven most of the revenue growth. The situation was particularly stark in 2013, as the 4.8% increase in chip business was apparently almost entirely due to a persistent DRAM shortage, with logic registering a paltry 0.4% growth for the year. The forecast for 2014 appears to be on track to repeat the experience of 2012 and 2013.
This weakness in chip sales reflects the listlessness of markets,including the heretofore healthy smartphone and tablet segments of mobile computing – both of which appear to be saturating and which are expected to plateau over the next 12 months. Pricing pressure is consequently increasing across the board.
Combined with market weakness is the unwelcome realization that we may be on the verge of seeing the repeal of Moore’s Law. The negative implications to 3P improvement and value-add thru feature growth by following the process curve into ever deeper geometries is obvious.
Taken together, these factors will markedly upset the current state of affairs in the custom chip sector, offering an opportunity for companies in each segment to completely overturn the current order. How they might go about doing this and the strengths and weaknesses of each segment that could help or hinder their attempts to re-invent themselves and adjust to the new reality of things is extensively discussed at the Vigil Futuri blog – http://vigilfuturi.blogspot.com.Share this post via: