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GM on BARRA’d Time

GM on BARRA’d Time
by Roger C. Lanctot on 07-25-2021 at 10:00 am

GM on BARRAd Time

Midway through her seventh year running General Motors it’s time to assess the legacy of CEO and Chairperson Mary Barra, the first woman to run an automobile company.  Of the 14 CEOs that have led GM, Barra’s term in office has been exceeded by only four of her predecessors:  Alfred Sloan Jr. (May 10, 1923 – June 3, 1946), Roger Smith (January 1, 1981 – July 31, 1990), John “Jack” Smith Jr. (November 2, 1992 – May 31, 2000), and G. Richard Wagoner Jr. (June 1, 2000 – March 30, 2009).

Barra stepped onto the world stage as the industry and GM were being whipsawed by technology shifts including electrification, autonomous driving, connectivity, and mobility.  She arrived in the wake of the revelations of Volkswagen’s use of so-called “defeat devices” to pass emissions tests for its diesel vehicles and on the eve of GM’s own scandal in the form of failing ignition switches.

Volkswagen would face billions of dollars in fines, customer compensation, and thousands of vehicle buybacks as well as other measures and two of its senior most executives faced arrest and will eventually stand trial. VW’s “defeat” software was ultimately found to have been deployed in 11M cars, 500,000 of them in the U.S.

GM’s ignition switch failures, which would be implicated in more than 100 fatalities and lead to the recall of 29M cars, resulted in the firing or departure of a couple dozen GM executives and a $900M fine. Both scandals were highlighted by awkward Congressional testimony.

Barra’s deft handling of the ignition switch crisis would serve as a defining moment for her and GM.  She learned immediately from her Congressional testimony in the Spring of 2014 that just as GM leadership that preceded her was able to dodge responsibility for mismanagement by filing for bankruptcy and turning to the government for help, she could dodge personal responsibility or even knowledge of the ignition switch failures, an assessment which the now-famous Valukas report supported.

The Valukas report effectively let GM off the hook allowing executives like Barra to feign ignorance while simultaneously seeking to repair or replace switches and keyfobs in millions of cars and compensating the handful of families whose claims were vetted and approved by an independent auditor.  Barra was able to assert a corporate recommitment to building safe vehicles even while working to overcome a broken corporate culture of which she was a product.

The results of the GM ignition switch debacle represent the foundation stone of Barra’s legacy: Plausible deniability.  Coined by the CIA in the 1960’s – according to Wikipedia – the expression “plausible deniability” describes “the withholding of information from senior officials to protect them from repercussions if illegal or unpopular activities became public knowledge.”

Of course, in Barra’s case plausible deniability refers to the plausibility of Barra or other senior managers not being aware of the flawed ignition switch either during its development, its deployment, or its use in millions of GM vehicles over nearly two decades.  It is especially noteworthy that Barra pulled off the plausible deniability act in front of Congress in spite of the existence of GM’s OnStar connected car technology – which is triggered by violent car crashes and provides GM engineers with valuable diagnostic data.

Where VW sacrificed senior leaders, some of whom accepted responsibility for decisions leading to the diesel scandal and others of whom still face criminal trials, GM avoided the most severe sanctions and suffered minimal public opprobrium.  Thanks to the bankruptcy, Barra was able to play word games about “old GM” and “new GM” despite the fact that she was a physical manifestation of the old GM.

From here, Barra proceeded to carve up GM, slashing its international presence by exiting multiple markets, most notably Europe by selling off Opel – a division that had been in GM’s brand portfolio for 100 years – to PSA, now known as Stellantis.  Notably, while GM was selling and exiting, PSA was buying – adding Opel and FCA – thereby vaulting the company into position as the fourth largest auto maker in the world based on vehicle sales.

With the sale of Opel and various other market moves GM’s global market share plunged and its rank fell to sixth, behind Hyundai.  Meanwhile, GM took a $500M stake in Lyft, launched its Maven car sharing service, and acquired in Cruise, an autonomous robotaxi startup.

The Lyft stake was intended to set the stage for an app integration with Cruise that failed.  Maven failed and shut down.  Cruise, alone, appears to be making progress albeit with a $250M/quarter burn rate that is likely to be magnified now that the division is manufacturing its own vehicles to support a robotaxi service with a flawed business model.

All of this points to Barra’s second key legacy.  The incredible shrinking GM.  GM’s vehicle sales have declined steadily for the last four years.  This shrinkage follows steady growth in the years preceding Barra’s arrival.

In spite of this apparent decline in vehicle sales, GM’s stock price has been on the rise.  Which brings us to Barra’s third legacy – runaway CEO compensation.

With $23.6M in compensation in 2020, Barra is richly rewarded predominantly in stock and stock options.  Barra’s total compensation includes $13.09M in stock awards and $3.75M in stock options.  So, it is perhaps hardly shocking that the CEO’s focus is on GM’s stock.

Four years before being named CEO, Barra – as executive vice president, global product development and global purchasing and supply chain – told a Fortune conference that her guidance to product developers at GM was “No more crappy cars.”  The directive reflected Barra’s odd role as simultaneously of GM and seemingly external to GM.

The title she held at the time of that quote, though, is a jarring reminder that the decision making related to the failed and failing ignition switches was occurring and had occurred on her watch.  In other words, GM was still making crappy cars even as she was speaking those words and since.

Perhaps Barra sees her role as a shareholder advocate – now that she holds GM stock worth as much as $70M or more, depending on whose estimate you rely on.  GM’s stock-centric compensation seems to have created a value proposition whereby any decision that juices the stock takes priority over all others which might include safety or customer satisfaction.

It was GM’s single-minded pursuit of profit that brought the ignition switch to the market in the first place.  According to some involved in the decision, the choice was between a 57-cent switch and one costing as much as a dollar more.  Multiplied by 29M vehicles, the contribution to the bottom line and performance bonuses was clear – at the time.  In retrospect? – not so much.

In its latest meeting, GM’s Board rejected a proposal to tie compensation to greenhouse gas emissions targets.

In the midst of the recovery from the pandemic, during which GM implemented company-wide pay deferrals, Barra got a pay raise.  The final piece of Barra’s legacy is this seeming disconnect between Barra and GM employees, dealers, and GM customers.

Barra’s “No more crappy cars,” while a welcome sentiment for some GM customers, dealers, and engineers, marks her as a critic of the very organization that cultivated and has so richly rewarded her.  Does she feel the pain of her colleagues or is she inflicting it?  She certainly isn’t easing that pain.

To review, at the seven year mark, GM Chairperson and CEO Mary Barra’s legacy consists of:

  1. Plausible Deniability
  2. Incredible Shrinking GM
  3. Runaway Stock-based Compensation

GM, under Barra, has made a lot of noise around its Ultium-centric electrification strategy.  Of course, every auto maker in the industry has made bold statements regarding EV investments and vehicle launches.  The EV initiatives are counterbalanced by GM’s announced intention to almost completely cease making and selling sedans.

GM has some promising initiatives in commercial and delivery vehicles – but nothing that offers a breakthrough in technology or form factor – more of a me-too offering. GM has notably failed to create a Tesla killer, which would presumably arrive with a Cadillac badge.  As the Talking Heads sang: “Still Waiting.”

Car makers from Renault to Stellantis to Hyundai, Volvo, Daimler, and Honda are notching technology breakthroughs in vehicle form factors, user experiences, safety, or autonomous operation.  GM has Super Cruise, an elevated stock price, and a heavily compensated CEO. After seven years, GM employees, dealers, and shareholders have to ask if that is enough.

Barra talks a good game regarding zero emissions and zero fatalities – but in the end, she has no skin in the game. What GM dealers, customers, and employees are left with is zero accountability.


ASML- A Semiconductor Market Leader-Strong Demand Across all Products/Markets

ASML- A Semiconductor Market Leader-Strong Demand Across all Products/Markets
by Robert Maire on 07-25-2021 at 6:00 am

asml logo 20120410 1

– Strong demand across logic/memory & leading/trailing edge
– Customers want units fast-no time to test
– The main question is can ASML ramp to meet demand?

Revenue & Earnings low due to systems being rushed to customers
ASML reported Euro 4B in sales and Euro 1B in net income which while within guidance was on the surface low as systems were shipped prior to being tested which meant the revenue can’t be booked until they are tested at the customer site, which delays revenue recognition by a quarter.

This delayed revenue is not the real news, the real news is that customers as so desperate they want systems faster than the normal procedure.

Obviously chip customers are clamoring for capacity and ASML is trying to do their part to accommodate the situation.

ASML had expected business to be up 30% in 2021 it now looks like business will be up 35%

Orders are off the charts
Orders were Euro 8.3B with Euro 4.9B of that for EUV. This is up huge from q!’s Euro 4.7B. Memory business was up from 24% to 29% of orders. Guidance is for Q3 to be Euro 5.2B to 5.4B with gross margins of 51% to 52%.

Dry tools staging a comeback
Perhaps the best evidence of how broad based the chip shortage is, is that demand for “dry” ArF systems is growing and the company is going to unusual lengths to satisfy that unusual demand. These systems are used in older technology fabs at large line width technology certainly not anything close to leading edge.

This likely addresses autos, appliances, IOT and other mid to trailing edge technology

EUV for memory starting up
We are starting to see the early stages of EUV for memory applications. We think this could be very fortuitous timing in that memory demand could help make up for any slow down in business driven after the near term shortage and panic abates. We don’t expect this higher level of business across the board to last forever as the shortage will eventually be filled.

Having memory ramp up its need for EUV would create a very nice “backfill” of business as shortage driven business subsides. This would also be good to help fill any potential slowness created by any delays or other issues with high NA EUV.

Ramping as fast as possible
The main risk we see with ASML right now is just one of being able to ramp as quickly as demand. Lenses and other specialty components simply can’t be rushed to have capacity increase at the drop of a hat. ASML has a number of key suppliers, such as Zeiss, and there a limited number of Germans with the requisite skill sets and a limited number of the highly complex machines used to make the lenses.

As we have pointed out several times before, its a lot like trying to increase the supply of 15 year old single malt scotch. There are many time constraints.

Despite the difficulty ASML seems to be doing a very good job of expediting and prioritizing what they can. Its not so much an allocation of money as it is an allocation of resources which are more limited than money.

Right now, the lack of being able to ship to China is more of a blessing in that ASML is barely able to keep up with existing demand without more customers.

Intel likely ramping EUV
The US was only 3% of business last quarter and doubled to 6% this quarter which is still miles behind Taiwan at 36% and Korea at 39% and also trails China (non EUV) at 17%. But we would take this as a sign that Intel could be taking more EUV tools finally.

Collateral Calls
We would expect the rest of semiconductor equipment makers to report similarly strong business and orders. Perhaps not as huge as ASML but very strong upside as the demand appears very broad based and not just EUV.

Litho systems tend to lead dep and etch and others systems by a couple of quarters given lead times but in the current panic situation its highly likely that chip companies are just ordering anything that isn’t nailed down less they get stuck at the end of the line.

The Stocks
ASML trades at a very high but well deserved , monopoly like multiple. Business is not slowing any time over the next several quarters and will likely extend over a longer period than other semiconductor equipment companies due to the memory adoption of EUV which will not drive the dep and etch companies as much.

We remain concerned that the stocks are fully valued and have a hard time breaking through a somewhat plateau valuation over the last several months. Although we expect very strong earnings and orders from all semiconductor equipment companies we don’t know if we will see a corresponding increase in stock values.

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

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Podcast EP30: Interview with Tony Pialis, Alphawave IP

Podcast EP30: Interview with Tony Pialis, Alphawave IP
by Daniel Nenni on 07-23-2021 at 10:00 am

Dan is joined by Tony Pialis. Tony co-founded Alphawave in 2017 and has since served as its President and Chief Executive Officer. The journey of Alphawave is discussed, including differentiation, strategy and the IPO as well as a look to the future.

Tony co-founded Alphawave in 2017 and has since served as its President and Chief Executive Officer. Tony has extensive experience as an entrepreneur in the semiconductor industry, having co-founded three semiconductor IP companies, including Snowbush Microelectronics Inc, which was sold in 2007 and is currently part of Rambus. He also founded V Semiconductor Inc. which was acquired by Intel in 2012 and Tony served as Vice President of Analog and Mixed-Signal IP at Intel between 2012 and 2017.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


Architecture Exploration with Miribalis Design

Architecture Exploration with Miribalis Design
by Deepak Shankar on 07-23-2021 at 6:00 am

AE1

Architectural exploration is a vast area of engineering design. It starts with the planning phase where the designer will have the list of requirements from the customer and the rough architecture most likely on a paper. Next is to assemble the model and conduct variety of trade-offs for optimization and functional studies to meet the specified requirements. It may technical or business requirement or the cost. Architecture expiration code now goes to three states:

  1. a) Generates documentation.
  2. b) Development of the specification either by an internal team or an external partner which can be at the semiconductor level embedded systems or software level.
  3. c) Provides a platform for early software development, field testing, integration testing and a variety of other requirements that come along the product development flow.

Fig 1: Architecture exploration flow diagram from Mirabilis Design

Figure 1 displays an architectural exploration flow diagram. A typical system is going to consist of three parts: a) communication b) computation and c) scheduling.

Communication typically includes the topology, fabric, busts, and knobs. It may be at a board, a network or a semiconductor. For instance, the first part of the image in figure 2 shows different communication templates like the ring, shared bus, and a complete embedded system distributed network. The second part displays a whole variety of devices that would exist on the system like Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Central Processing Unit (CPU), Dynamic Random Access Memory (DRAM) etc. Finally, the last part exhibits different types of scheduling/arbitration flow control.

 Fig 2: Components of a System Architecture.

There are multiple architectures available. Three things must be taken into consideration before choosing of an architecture.

  1. a) The traffic
  2. b) The workflow and
  3. c) The specified requirement the designer need to attain like lower latency, higher throughput, lower energy, lower power or the overall cost.

Based on these criteria’s one can evaluate which architecture is more suitable for a particular application. A particular product for instance a SSD system, may have different architecture requirements. Depending on whether it is going into the mobile or the data center or the desktop the form factor, cost, performance, and throughput can be completely different for the same product.

Architecture exploration can be used across every application space where electronics is used. For instance, it can be used for a card network, a rocket, or a semiconductor component like a power processor.

Requirements for architectural exploration

Architecture exploration starts from an early conceptual stage and can goes down all the way through the product development flow. This can be explained with the help of a diagram.

Fig 3: Architectural Exploration Methodology using System Modeling software such as VisualSim Architect

Due to early analysis of requirements, the designer need not be worried about components. At this stage the key concern is how to translate the requirements into an engineering market. Next step is to focus on the performance and power optimization, to reckon the trade-offs, for instance the failure and functional analysis, security, and a variety of other attributes. The designer exactly can detect what is going to be the minimum latency or the highest throughput that can be achieved. After this point, hardware and software partitioning is done in order to split the data across multiple subsystems or across multiple IPs and on a chip or across multiple boxes. After dividing the portions of software and hardware, select different components, schedule the arc tosses and assemble a complete system. If there is a c code or an emulator that has some technology at this point, then that can be integrated to create a single environment.

Architecture Exploration phases

Architecture exploration can be divided into four parts.

  1. Model based System Design
  2. Electronic System-Level Design
  3. Virtual Prototyping
  4. Hybrid Prototyping

Fig 4: Architecture Exploration Phases

Model Based System Design can be applied to vehicle networking, mission level, networked systems, and data centers. In vehicle networking, it connects the internals like the gateways, the network etc. that are within the car and the externals systems like the Wi-Fi, satellite communication etc., at the same time into one model. Similarly, at mission level, you must build a network that connects multiple aircrafts, satellites, and ground stations together. In case of networked systems data centers, one need to connect the IOT systems or semiconductor vendors, chips together into a single model. So, the goal is to provide a solution, not just about what’s inside of the chip or inside of the box but also what is the performance when one communicates with the datacenter. This can be done at early stage of design process.

For electronics system level design, one can design the semiconductor, the hardware, and the software like designing of the artificial intelligence score or to put an entire chip together or to integrate multiple systems and boards together. So, looking at end to end of every aspect is important to get a good quality product.

Virtual prototyping is using of something that already exists in the system and the designer want to use it onto a new design. It may be a software or modify an old software to work on a new design. Or the designer has decided on a design, and he want to check whether the diagnostics is sufficient. Or even if he wants a platform to run the software and check the functionality. The designer can evaluate performance improvement or power saving from software update. For example, on an Autosar platform in a vehicle, simple rescheduling can reduce software usage by up to 35-40%. Virtual prototyping is also useful for developing software on system model and instruction set simulator. In the same platform and the system, one can integrate the instruction set and the simulators to run the OS and the software such that some early software simulations or even early software development can be done. Lastly, security, redundancy and functional safety are taken care of.

Hybrid prototyping is taking up of the existing IP or RTL and connecting it onto a board or providing a design under test. So, the designer takes a hardware system i.e. an emulator for example while the test environment can be a network or other boards on the system or system level modeling environment which is part of the architecture model and can study the waveforms or the expected response times.

All these phases are required in a product development flow. The designer may give higher priority to one and verify the check marks or test cases in others. All these need to be available in order to say that the environment supports artificial or architecture exploration.

Conclusion
The designer can see a variety of designs starting from a high network to a distributed system to semiconductors to IP and finally at power and failure analysis. One of the key aspects is everything should be done within the same environment. Architectural exploration of the entire project is critical to the success of it. It eliminates any room for errors in later stage. It will give a clear picture of various parameters values and analysis reports in details that will enable us to rectify the faults if any at an early stage. It saves huge amount of money, effort, and time of the client. Besides, making any change to the hardware components at later stage is not feasible. The designer may need to change the algorithm itself. In the product proposal phase the specification is quickly validated to meet the requirements. In the product specification the architecture is optimized to get the best solution. Visualsim provides a collaborative platform to continuously verify that the changes meet the requirements. The platform is expected to provide modeling, exploration and collaboration solutions for semiconductors, digital electronics and Embedded Systems. It is to ensure the right design for the products.

WEBINAR: Architecture Exploration of System-on-chip using VisualSim Hybrid RISC-V and ARM Processor library

Authors
Deepak Shankar is the founder of Mirabilis Design, Mr.Shankar has over two decades of experience in management and marketing of system level design tools. Prior to establishing Mirabilis Design, he held the reins as Vice President, Business Development at MemCall, a fabless semiconductor company and SpinCircuit, a joint venture of industry leaders Hewlett Packard, Flextronics and Cadence. He started his career designing network simulators for the US Federal Agencies and managing discrete-event simulators for Cadence. His extensive experience in product design and marketing stems from his association with the EDA industry in multifaceted roles. An alumnus of University of California Berkeley with an MBA, he holds a MS in Electronics from Clemson University and a BS in Electronics and Communication from Coimbatore Institute of Technology, India.

Anupurba Mukherjee obtained her B.Tech in Electronics and Communication Engineering from University of Engineering and Management, Kolkata in 2019. She is the Product Market Engineer at Mirabilis Design Incorporation, Chennai, India.

Also Read:

CEO Interview: Deepak Shankar of Mirabilis Design

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WEBINAR: Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)


A Custom Layout Environment for SOC Design Closure

A Custom Layout Environment for SOC Design Closure
by Tom Simon on 07-22-2021 at 10:00 am

custom layout environment

Throughout the process of physical design and verification there are many groups working on the design. Most often these groups are working independently or in parallel but separately, using their own specialized tools, such as P&R, DRC, custom layout, DFM, etc. At the end of the process there is an inevitable requirement for all these teams to work together on the same data at the same time. This mandates that they step out of their siloed tool environments and share the design in its totality. This has created the need for a tool that can load the entire assembled design and then interface with critical verification tools. It is here that all levels of abstraction, such has standard cells and custom blocks can be expanded so that the full geometry is accessible from top to bottom. It is also here where the final necessary changes can be made to reach tape out.

Custom Layout Environment

To meet this need Siemens EDA offers the Calibre DESIGNrev tool. It serves as a common tool that can be shared across all stake holders and used to resolve the final issues before tape out. Although in theory the design can loop back through the development flow, in reality these cycles are too long and collaboration is much more difficult. With a tool like Calibre DESIGNrev there is an opportunity to create user environments that help accelerate the overall process.

As part of this user environment, almost every aspect of how the tool looks and works can be configured to achieve several goals. Siemens spells this out in an article titled “A custom layout environment improves productivity across IC design and verification flows”. They developed the customization features in Calibre DESIGNrev to help with a number of things. First off, they make it easier for users with different backgrounds to use.  Customizations help ensure that corporate or project based design standards are followed. At the same time individual users can tailor their environment to make operations more efficient. Lastly scripts can be created to handle new tasks or automate existing ones.

The Siemens article goes over each of the main configuration features. Tool preferences allow day-to-day things like ruler snapping, grid settings and tool appearance to be saved. Layer properties, like color, fill, connectivity, names, etc. can easily be set and saved. Keyboard shortcuts are another customizable feature. Lastly, they talk about how the reader can be configured to handle non-standard objects in the designs.

It is not enough to be able to have settings for each user. Calibre DESIGNrev has a system built in to allow the setting to be specified hierarchically for use across the company, a project or a team. There is the ability to enforce specific settings to ensure consistency. The various saved configurations can be shared across teams, projects and entire enterprises.

There are tight linkages with the physical verification flow that allow for rapid resolution of late stage issues. Siemens talks about how this added efficiency helps to decrease turnaround time and shorten time to tape out. The full article is available for download at the Siemens website.

Also Read:

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RealTime Digital DRC Can Save Time Close to Tapeout

From Silicon To Systems


Magnetic Immunity for Embedded Magnetoresistive RAM (eMRAM)

Magnetic Immunity for Embedded Magnetoresistive RAM (eMRAM)
by Tom Dillinger on 07-22-2021 at 6:00 am

coil interaction

Previous SemiWiki articles have discussed the introduction of embedded Spin-Transfer Torque Magnetoresistive RAM IP from GLOBALFOUNDRIES, as an evolution replacement for non-volatile embedded flash memory. (link, link)

Those articles described the key features of STT-MRAM technology, but didn’t delve into a key reliability concern – namely, the degree of “immunity” of the MRAM bitcell array to external magnetic fields.  These fields could disrupt the magnetic polarization of the bitcell, if the field magnitude was sufficient to overcome the coercivity of the magnetic materials used in the bitcell tunnel junction (MTJ).

Note that these magnetic fields could originate from sources applied outside the SoC package – e.g., from the earth’s magnetic field, or from a malicious attempt to perturb the non-volatile stored data.  In addition, the MTJ will be exposed to magnetic fields originating with the package itself – e.g., from an inductive loop coil fabricated on the die, part of an LC-tank circuit used in an oscillator or SerDes IP macro.  It is crucial to understand the magnetic immunity of an eMRAM IP array when exposed to fields from either of these sources.

There are two definitions of magnetic immunity, whether the array is in “standby” (SMI) or “active” (AMI) mode – active is the more critical.

At the recent 2021 VLSI Symposium, Vinayak Bharat Naik, MRAM lead at GLOBALFOUNDRIES, provided results of magnetic immunity experimental analysis for MRAM arrays fabricated in the 22FDX-SOI process technology.[1]  Note that this technology also has very attractive RF device characteristics – thus, there may be on-die RF IP with inductive elements that emanate significant field magnitudes.  The rest of this article highlights the insights in Vinayak’s presentation on MRAM magnetic immunity.

Background

Briefly, a STT-MRAM bitcell consists of three key material layers, commonly in a vertical configuration – i.e., a “perpendicular” magnetic tunnel junction (MTJ).  The MTJ is comprised of:  a “fixed” (or reference) magnetic polarization orientation material;  a thin (tunnel) dielectric;  and, a “free” magnetic material whose polarization can be switched by the write current direction through the MTJ bitcell.  The write current needs to be of sufficient magnitude and duration.

After the write cycle, the resulting states of the bitcell are “parallel” (low read cycle series resistance) or “anti-parallel” (high read cycle series resistance), referring to the magnetic orientation of the two layers on either side of the tunnel junction, as illustrated below.

The figure above provides a comparison of the key features of the STT-MRAM bitcell, relative to embedded flash (to achieve suitably low PPM failure rates):

  • endurance (# of read/write cycles)
  • retention (non-volatile array storage)
  • read/write cycle performance
  • cost

All of these features need to apply over stringent environmental conditions – e.g., -40C to 125C – corresponding to the industrial applications for the SoC with the eMRAM IP.

Vinayak provided the results of a stress test consisting of a large number of iterative write-read cycles applied to the 40Mb 22FDX MRAM array depicted above.  (The temperature corner of -40C is the most critical.)  With ECC applied to the memory data operations, using the data + ECC bits macro architecture shown above, all “raw” data errors were corrected – i.e., the bit error rate (BER) was reduced to zero.

The MTJ is fabricated as part of the BEOL fabrication process steps, as shown in the TEM cross-section above.  The high-temperature FEOL steps have been completed.  Yet, it is imperative that the MTJ functionality is not impacted by subsequent exposure to elevated temperatures, such as solder reflow for die attach.  Vinayak also shared data that showed no increase in the BER after 5 reflow cycles of 260C (e.g., 40-80 seconds above 220C).

Magnetic Immunity to External Fields

As the basis for the non-volatile MTG states is the coercivity of the materials to an external magnetic field, the magnetic immunity (MI) of the STT-MRAM array is a new reliability parameter, not applicable to embedded flash.

As mentioned above, the external field could originate from outside the SoC package.  Vinayak showed the experimental setup and MI analysis results applied to an STT-MRAM testsite.  The figures below show the test fixture and illustrate that the (ECC-corrected) memory write-read BER was zero, with an active MI greater than 250 Oe.

Parenthetically, Vinayak also highlighted that the anisotropic nature of the magnetization domains within the MTJ layers suggests that the angle of incidence between the external magnetic field and the STT-MRAM testsite surface could affect the coercivity.  The figure below confirms this effect, as an angle of 45degrees between field and surface had the lowest MI.

Also, Vinayak noted that the MI will increase for smaller diameter MTJ bitcells, ensuring that STT-MRAM technology will continue to be attractive with subsequent process scaling.

For reference, here are some representative values of magnetic intensity, to compare to the MI target of >250 Oe:

  • earth’s magnetic field: 5 Oe
  • refrigerator magnet: 50 Oe
  • electromagnet in a junkyard for lifting cars: ~10,000 Oe
  • clinical MRI scanner: ~5,000 – 30,000 Oe

Vinayak briefly described the importance of integrating a “magnetic shield” material into the SoC package for embedded STT-MRAM IP, where exposure to high magnetic fields may be a concern.  For several years, GLOBALFOUNDRIES has had a strong collaboration with Everspin Technologies on MRAM development.  Everspin is shipping stand-alone MRAM parts.  “All Everspin products contain embedded magnetic shielding within their packages.” [2]

(For additional information on the types of shielding materials used and the degree of magnetic isolation provided, check out reference [3].)

On-Die Magnetic Immunity

There are two facets to magnetic immunity within the SoC die:

  • fields originating from an inductive coil, such as used in an LC tank circuit, contributing to STT-MRAM error rates
  • fields originating from the MTJ array itself, impacting the LC tank functionality

Vinayak shared analysis data showing the magnetic field strength from an inductive coil as a function of separation distance, as shown below.

For the model shown, a separation distance between a coil and MTJ array greater than 100um was sufficient to ensure the fields from the coil are below the target MI.  (A typical SoC design will likely contain multiple LC tank circuits, necessitating design-specific model analysis.)

The graph on the right above shows the magnetic field originating from an embedded STT-MRAM array, as a function of distance.  In the example above, the MRAM array field is very small, and thus would have negligible impact on the LC tank oscillation frequency.

Summary

Embedded STT-MRAM IP is emerging as a non-volatile storage replacement for eFlash at advanced process nodes, as exemplified by the offering from GLOBALFOUNDRIES in their 22FDX-SOI technology.  The performance, endurance, retention, and cost of STT-MRAM are extremely attractive.  (Architecturally, ECC bits added to the data word are required to achieve a zero bit error rate.)

The eMRAM does introduce a new reliability concern – the “magnetic immunity” of the array to external magnetic fields, either from outside the SoC package or from inductive circuits on the die.  The package composition may need additional magnetic shielding, if the potential field magnitude could exceed the MI.  For on-die inductors, suitable spacing to the eMRAM array will ensure the MI reliability limits are not exceeded.

I would encourage you to review the MI analysis techniques and results that GLOBALFOUNDRIES presented at the 2021 VLSI Symposium.  Also, here is a link to an informative GLOBALFOUNDRIES webinar on embedded NVM IP development – link.  

-chipguy

 

References

[1]  Vinayak Bharat Naik, “STT-MRAM: A Robust Embedded Non-Volatile Memory with Superior Reliability and Immunity to External Magnetic Field and RF Sources”, VLSI Symposium, 2021, paper T12-2.

[2]  Everspin Technologies, “Magnetic Field Immunity of Everspin MRAM”, whitepaper EST02880,  www.everspin.com/file/784/download .

[3]  https://magneticshields.co.uk/technical/magnetic-shielding-how-does-it-work

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Electronics Recovery Mixed

Electronics Recovery Mixed
by Bill Jewell on 07-21-2021 at 2:00 pm

Electronics Recovery Mixed

Electronics production continues to recover from the COVID-19 pandemic. However, the recovery is mixed by country. The chart below shows three-month-average (3/12) change versus a year ago in electronics production by local currency for key Asian countries. China was averaging about 10% growth prior to the pandemic. After a sharp drop in early 2020, China recovered to about 10% growth. June 2021 3/12 growth was 12%. South Korea electronics production was largely unaffected by the pandemic. 3/12 growth never dropped below 8% in 2020 and was a strong 19% in May 2021. Taiwan also experienced minimal disruption, with 3/12 change above 4% in each month of 2020. Taiwan 3/12 change has averaged about 10% in 2021. Vietnam had pandemic related fluctuations in 2020 but bounced back to 13% 3/12 growth in June 2021. Japan electronics production has been weak for several years. 3/12 change dropped to negative 18% in September 2020. Japan recovered to 5% 3/12 growth in May 2021.

The United States and Europe had more COVID-19 cases relative to their population than the Asian countries, according to the World Health Organization (WHO). The U.S. and Europe each had over 100 COVID-19 deaths per 100,000 people. Most major Asian countries had fewer than 10 COVID-19 deaths per 100,000 people. Some exceptions were India at 30, Malaysia at 22 and Japan at 12.

Despite the relatively high number of COVID-19 cases and deaths, U.S. electronics production did not experience a significant slowdown. U.S. 3/12 change in 2020 never dropped below a 1% decline. Production for the year 2020 was up 3.6% from 2019, the highest annual growth since 2008. 2021 3/12 change has been about 8% each month, with May up 9%.

The United Kingdom (UK) officially withdrew from the European Union (EU) in January 2020 in a process known as Brexit. Thus, Europe had to deal with the effects of Brexit as well as COVID-19. The 27 EU countries (EU 27) have shown strong 3/12 growth of over 24% in each month of 2021 after declines in most months of 2020. UK electronics production had 3/12 declines in every month of 2020, with the worsts months in May and June at a 19% decline. The UK has recovered in the last few months, with May 2021 3/12 growth of 15%.

Two key electronic products are PCs and smartphones. These are relatively mature products with flat to declining unit shipments over the last few years. However, these products experienced totally different trends during the pandemic. Based on data from IDC, smartphone units versus a year ago declined 12% in 1Q 2020 and 16% in 2Q 2020 primarily due pandemic-related production cuts in China. Smartphone units recovered to 26% year-to-year growth in 1Q 2021. Estimates based on Canalys data in 2Q 2021 show 10% growth versus a year ago. Smartphone units declined 5.8% in the year 2020 versus 2019. In May 2021 IDC forecasted 7.7% growth for smartphone units in 2021, slowing to 3.8% growth in 2022.

PC unit shipments had an entirely different trend. IDC data shows 1Q 2020 units declined 8% from a year ago, largely due to pandemic related supply issues. PCs bounced back robustly with 2Q 2020 up 14% year on year. Growth has been above 10% since, with 2Q 2021 up 13%. For the year 2020, PC units were up 12%, the strongest annual growth in ten years. PC demand has been driven by pandemic trends. Many countries had stay-at-home orders or recommendations for several months of 2020. People had to rely on PCs connected to the internet for work, education, and entertainment. Many households without PCs acquired them, often paid for, or subsidized by, employers or school systems. Many households with PCs upgraded with new models and/or added additional units. IDC expects strong PC growth to continue in 2021, with their May 2021 forecast for 18% growth. IDC expects the PC market to correct in 2022 with a 3% decline.

To understand the effects of the pandemic on the electronics industry, it is helpful to compare data for 2021 to the pre-pandemic levels in 2019. Other factors in addition to the pandemic contributed to these trends. Continuing trade friction between China and the U.S. led to some production shifting out of China to other Asian countries. Brexit affected electronics production in the UK versus the EU.

The most substantial change in electronics production for January through May of 2021 compared to the same period in 2019 was in South Korea, up 37%. South Korea saw little disruption in electronics production due to the pandemic. It also benefited from some production shifting from China to South Korea. China was up 26%, as it quickly recovered from pandemic related slowdowns in early 2020. Taiwan was up 15% and Vietnam was up 11% as both countries had relatively minor pandemic-related production disruptions and both benefited from production shifts from China. Japan was up 1%, reflecting its weak electronics production over the last several years.

EU 27 electronics production in January-May 2021 grew 23% versus two years ago, while the UK declined 8%. This likely reflects some Brexit-related production shifts from the UK to the EU countries. The U.S. was up 9%, the strongest growth in over a decade. Despite relatively high COVID-19 rates in the U.S., electronics production was largely unaffected. This is likely due to highly automated production in the U.S. compared to labor intensive production in China and other countries.

The difference in the PC and smartphone markets is highlighted by comparing units shipped in the first half of 2021 compared to the first half of 2019. PCs were up 35% while smartphones were only up 1%.

The COVID-19 pandemic is far from over, with WHO showing rising cases and deaths in the last several weeks. However, the major disruptions to society and industry are mostly over. The electronics industry is generally back on track.

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WEBINAR: Maximizing Exit Valuations for Technology Companies

WEBINAR: Maximizing Exit Valuations for Technology Companies
by Daniel Nenni on 07-21-2021 at 10:00 am

Silicon Catalyst Exit Webinar

I had the opportunity to speak with Pete Rodriguez and Alain Labat in regards to the upcoming webinar on M&A. I have worked with both Pete and Alain in the past so I can tell you personally that this event will be well worth your time. This is truly an all star cast with a collective experience base with billions of dollars worth of M&A behind it. This is really an all hands on deck call for entrepreneurs, absolutely.

“Maximizing Exit Valuations for Technology Companies”
July 28, 2021 – 11:30 to 1pm Pacific

Register Here

The webinar will kick-off with a short presentation by Pete Rodriquez, CEO of Silicon Catalyst, detailing his deep experience with mergers and acquisitions, from both sides of the table. Pete’s presentation will be followed by a panel session discussion with CEO’s reviewing their exit stories, and will be joined on the panel by investment professionals, including noted M&A expert Warren Lazarow, former chair of O’Melveny’s Global Corporate Department and co-chair until February 2021. Mr. Lazarow has been included on several occasions in Forbes Magazine’s Top 100 Dealmakers Worldwide in the technology sector.

Topics to be discussed during the webinar:
• Key elements needed for a strategic exit – both technology & business aspects
• Product differentiation and scarcity of technology
• Preparation and strategy for an exit
• Timing, timing & timing
• Selecting and hiring the right banker/advisor
• Orchestrating a competitive process

Agenda – Wednesday July 28th, 2021 11:30am

Introductions
Pete Rodriguez – M&A advice

Panel Session discussion, with Q&A from attendees

Moderator
Pete Rodriguez, Silicon Catalyst, CEO

Panelists
Roger Fawcett, ex-CEO of Omnitek, acquired by Intel
Alain Labat, Managing Director, Harvest Management Partners
Warren Lazarow, Partner, O’Melveny
Yvonne Lutsch, Ph.D., Investment Principal Robert Bosch Venture Capital
James Pond, Ph.D., ex-CEO of Lumerical, acquired by Ansys

See press coverage of the acquisitions of Omnitek (Intel) and Lumerical (Ansys)
https://newsroom.intel.com/news/intel-acquires-omnitek-fpgas/#gs.5qj4pc
https://www.ansys.com/news-center/press-releases/03-05-20-ansys-photonic-simulation-leader-lumerical-sign-definitive-acquisition-agreement

Registration for this zoom webinar can be made at: Register Here

About Silicon Catalyst
Silicon Catalyst is the world’s only incubator focused exclusively on accelerating solutions in silicon (including IP, MEMS & sensors), building a coalition of in-kind and strategic partners to dramatically reduce the cost and complexity of development. More than 400 startup companies have engaged with Silicon Catalyst since April 2015, with a total of 38 startup and early-stage companies admitted to the incubator. With a world-class network of mentors to advise startups, Silicon Catalyst is helping new semiconductor companies address the challenges in moving from idea to realization. The incubator/accelerator supplies startups with a path to design tools, silicon devices, networking, access to funding, banking and marketing acumen to successfully launch and grow their companies’ novel technology solutions. The Silicon Catalyst Angels was established in July 2019 as a separate organization to provide access to seed and Series A funding for Silicon Catalyst portfolio companies.

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A Hardware Security Standard Advances

A Hardware Security Standard Advances
by Bernard Murphy on 07-21-2021 at 6:00 am

security min

Security is a slippery topic. We all agree that “something should be done”, but most of us are waiting for someone else to lead the way. There’s no shortage of proprietary solutions, though given the distributed nature of the problem it’s difficult to see how those separately or collectively can rise to the occasion. What we really need are standards and then either regulation or market forces to drive non-compliant providers out of business. Accellera has taken a step in this direction with their first release of the standard “Security Annotation for Electronic Design Integration”. Otherwise known as SA-EDI, informally SADIE, a new hardware security standard.

Where do you start?

When you think about it, the best place to start isn’t some kind of idealized technology or language. No matter how ingenious these proposals might be, new attacks by definition exploit weaknesses we haven’t considered. We don’t need a standard which will become obsolete as soon as some completely new exploit emerges. Instead, start with a list of all known exploits. Call these common vulnerabilities and exposures (CVE), which is what the Mitre Corporation did in building their list for software exploits. If a new exploit appears, just add it to the list, no matter how clever or different the technique it uses.

Next, dig into each exploit to find the underlying weakness(es) that made that exploit possible. Make a list of these and call it a common weaknesses enumeration (CWE). Again, Mitre Corporation have done this. In fact these guys have led the way so effectively in software, and have started to do the same thing for hardware exploits, that Accellera is following their approach quite closely, in philosophy, though Accellera calls their database the Security Weakness Knowledge Base. This can refer to multiple knowledge bases such as Mitre CWE as well as in-house databases.

Entries can be decorated with tags to specify product families in which attacks most commonly appear, revisions (since attacks also go through upgrades), and other useful info. So a part of the SA-EDI standard defines a structure for this knowledge base information. One very important tag lists the risks associated with a weakness using the familiar CIA (Confidentiality, Integrity, Availability) classification.

Annotating IPs

A goal for the standard is to promote development of checking technologies, but it can’t assume any particular style of checking. Assertions probably aren’t appropriate. But there are common factors in all such checks. One is information about what assets you want to protect. An example would be an encryption key. Assets aren’t necessarily just data. A watchdog timer is an asset to protect if you use it to trigger a safety or security check for example.

Then you need to indicate what attacks from the knowledge base might be relevant for each asset and what elements in the design (ports, interfaces, configurations) would be used in such an attack. These together with any security mitigations you might add form what the standard calls an attack point security objective (APSO).

SA-EDI is an annotation standard. The goal is to annotate the IP with this information. How you create that information is up to you. In the near term, this may be manual, with minimal scripting support. Annotation is handled through a side JSON file. I’ve seen some mention also of XML, presumably for IP-XACT support. The current bias seems to be more to JSON which I must admit is more human-readable than XML.

A quick sidebar on mitigation. If the IP developer knows there is a security weakness in their IP, why don’t they fix it? That might not always be appropriate. A local fix may be the least optimal solution to a security problem. The right place to fix a JTAG security problem is at the top-level, not in every individual IP instance that path touches. However the IP vendor should annotate that the test/debug path into their IP is a security weakness and should be addressed in integration.

SA-EDI and integration

With suitable tools (scripts or later more advanced tools) an integrator can verify the correctness of the delivered SA-EDI package, checking that the IP vendor didn’t skip some of the weaknesses they should have considered. Integrators can also adapt the annotation, dropping weaknesses they know won’t be a concern (they don’t plan to hookup JTAG for example). They can also add new weaknesses they want to consider, maybe based on an in-house knowledge base. Finally they run whatever security verification analyses they have available.

When can we expect tooling?

Synopsys, Cadence, Tortuga and OneSpin all have representatives on the working group. Tortuga is fairly closely involved with Mitre on their hardware list. So I have to believe work is progressing to develop tools/apps/extensions. That said, addressing a complete list is going to require a number of different technologies. Just looking quickly at the Mitre list for hardware:

  • Some checks relate to package completeness, eg missing documentation
  • Formal checks may work well in some cases, eg improper lock behavior after power state transition
  • Some may require fairly deep verification, eg DMA enabled too soon in boot phase
  • The list includes side-channel attacks but this is a very broad topic. I expect further division here
  • Functional verification tools are not going to address manufacturing and lifecycle management concerns

There’s some concern about simulation-based checks unless we develop a robust sense of coverage for security. Nevertheless I can see plenty of opportunity for more automation in support of the standard. Great start!

You can download the standard HERE.


EDA Flows for 3D Die Integration

EDA Flows for 3D Die Integration
by Tom Dillinger on 07-20-2021 at 6:00 am

future integration

Background

The emergence of 2.5D heterogeneous die integration using a silicon (or organic) interposer has enabled unique system architectures.  The term “More than Moore” has been used to describe the circuit density and cost advantages of leveraging multiple die in the package, the die potentially in different process technologies.  Specifically, the integration of High Bandwidth Memory (HBM) stacks has led to innovative product designs, with new memory hierarchy and coherence management approaches.

The efforts to develop “standard” (short-reach and ultra-short-reach) communication interfaces between the heterogeneous die will further promote integration efforts through die re-use.

The EDA tool/platform development required to enable advanced 2.5D integration was relatively minor.  There were existing “system-in-package” (SiP) tools for multi-die packages (on organic substrates), such as for the design of separate baseband and radio frequency functions.  The density of the redistribution layer interconnects is significantly higher in current 2.5D implementations, yet the additional EDA support for 2.5D package connectivity management, physical implementation, physical design verification, parasitic extraction, and electrical analysis did not involve the introduction of major new features.  Such is not the case for the newer 3D package technologies.

An Incremental Approach toward 3D Integration EDA Tool Support

At the recent VLSI Symposium, Vinay Patwardhan, Product Management Group Director in the Digital Design and Implementation team at Cadence, provided insights into the challenges of EDA support for 3D die integration, and the current platform status at Cadence.[1]  This article summarizes the highlights of his presentation.

Briefly, 3D packaging technology involves direct, vertical die-to-die attach at bond pad interfaces (i.e., without elevating microbumps).  The die orientation may be either face-to-face or face-to-back.  Through silicon vias (TSVs) are used to provide connectivity through the die, for face-to-back bonding and to the package substrate.  The technology for die bonding is evolving rapidly, currently enabling a connection pitch of ~1um.  The TSV density is also potentially very high, with ~5um pitch as the current implementation target.  (The supported TSV pitch depends strongly upon the aspect ratio of the via diameter-to-die thickness.)

Vinay divided his presentation into three sub-topics:

  • 2D-to-3D algorithm enhancements required for specific tools
  • tool-to-tool interdependencies and data interfaces (e.g., for rapid iterative design closure)
  • a “comprehensive” 3D design database and tool platform

The figure below illustrates these three areas.

Vinay described that Cadence has taken an incremental approach toward 3D integration enablement, focusing initially on the first two areas, while concurrently developing a common design platform.  The goal is to provide an evolutionary path for 3D designers, who are familiar with existing tools.

2D-to-3D algorithm features

Here are a couple of examples of 2D-to-3D tool algorithms features that Vinay described:

  • multi-die macro placement

A difficult problem for any placement algorithm is dealing with a (potentially large) number of hard IP macros in the design netlist, in addition to the very large number of standard cells.

As depicted below, a hard IP instance presents significant routing blockages, and typically has few pins.  As a result, a wiring-length and (coarse grid) wiring-track density congestion avoidance optimization will tend to place macros toward the perimeter of a floorplan area in a 2D placer.[2]

Yet, it is very likely that the hard IP macro is part of timing critical paths, such as the read access time through an on-chip register file or memory array.  For timing optimization, the macro should be placed among the related logic cells, despite the few nets involved.

Vinay provided a description of a new 3D placement feature, where hard IP is preferentially promoted to the top die, connected to the related logic through the physical assignment of die-to-die bonds, as illustrated below.

The Innovus implementation tool is “multi-die connectivity aware” as part of its optimization features, with die abstracts representing the different designs.

  • 3D system partitioning

An even greater issue with 3D integration design is the initial development of the overall system architecture partitioning between the different die – a task sometimes described as pathfinding.  (I had a professor who liked to say, “80% of all electrical design automation challenges are related to partition optimization.”)

Unlike the typical 2.5D design where existing HBM stacks and/or hard IP chiplets are incorporated into the architecture, the 3D system designer is likely working with a blank canvas.  The functionality needs to be optimally allocated to individual die to meet PPA and cost objectives.

Vinay described how the Cadence OrbitIO product has been extended to provide the system connectivity model and partitioning analysis features needed for 3D design exploration, as illustrated below.

The features added include support for bond and TSV alignment between die and the package substrate, with visualization of the hierarchical system configuration.  From the OrbitIO interface, the data exchanges to other tools are also shown in the figure above.

Tool interdependency features for 3D integration

In addition to 2D-to-3D tool algorithm/feature enhancements, Vinay highlighted that Cadence prioritized several key tool interdependencies that necessitated tighter integration, rather than data file export/import.

  • iterative design closure for ECOs

Of specific importance was the integration of the OrbitIO design environment with the Innovus physical implementation tool, such as to support rapid iteration design ECO closure.  The figure below shows the additional tool support provided between these two platforms.

  • I*R and thermal analysis closure

Another tool interdependency focus was extending the 3D capabilities of the power/I*R and thermal analysis data models.  Initial 3D power estimates are provided to the 3D thermal analysis engine, which sends thermal map values back to the I*R analysis for design closure, as depicted in the figure below.

3D Platform and ADK Enablement

As shown in the very first figure, the third phase of this EDA flow evolution will be to utilize a full 3D-enabled design database model, to further support inter-die optimizations.

One caveat that Vinay mentioned was the lack of a standard packaging Assembly Design Kit (ADK), analogous to the Process Design Kit (PDK) data that comprehensively represents the fabrication guidelines, electrical models, and design verification rules that define a silicon process.  Vinay provided the figure below to illustrate how he envisions an ADK would be integrated into 3D design enablement.

Summary

The evolution of advanced packaging technology to 3D die integration requires significant EDA tool investment.  In pursuing an incremental approach, Cadence has added 3D features to tools, and provided specific interdependent tool “tight loop’ iteration support.  The remaining verification and analysis flows utilize the data format exchanges shown above.  This approach provided full 3D enablement, building upon a mature design platform.

In the future, look for more varied system partitioning techniques, with 2.5D packaging technology integrating 3D configurations – similar to the use of HBM stacks, but with more complex 3D topologies.  And, look for increasing momentum behind the definition of an Assembly Design Kit, to accelerate this packaging technology innovation.

-chipguy

References

[1] Vinay Patwardhan, “Entering a new dimension with 3D-IC design – EDA perspective”, VLSI Symposium 2021, Workshop 2.6.

[2] T. Dillinger, VLSI Design Methodology Development, Prentice-Hall, 2019.

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