WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 487
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 487
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)
            
14173 SemiWiki Banner 800x1001
WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 487
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 487
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)

Circuit Simulation Challenges to Design the Xilinx Versal ACAP

Circuit Simulation Challenges to Design the Xilinx Versal ACAP
by Daniel Payne on 06-24-2021 at 10:00 am

One of the most unique acronyms that I learned about this past year is ACAP from Xilinx, which stands for Adaptive Compute Acceleration Platform. At the recent Cadence LIVE event, I had the pleasure of watching Pei Yao, a Xilinx senior staff CAD engineer, as she talked about the challenges of getting all the analog and mixed-signals parts of their SoC to meet PPA specifications. Here’s a block diagram to show all of the IP included in the Xilinx Versal family of chips:

xilinx versal acap min
Source: Xilinx

The scalar engines are popular Arm-based cores, the adaptable engines are what we used to call a classic FPGA with memories, and the intelligent engines are customized for both AI and DSP functions. All of these high-level IP blocks communicate with a Network-on-Chip (NoC), and then the IP for IO comes in a dozen varieties.

7nm Design Challenges

Yao went through a list of design challenges, and the Versal chips used the 7nm process:

  • Process variation effects increased
  • RC interconnect delays increased
  • More thermal and reliability concerns
  • Sheer design complexity
  • Increased number of IP blocks
  • Clock rate increased
  • Noise and coupling issues

To complete their transistor-level analysis with these design challenges, the circuit simulation run times increased, the capacity required for circuit simulation increased, and more CPU resources were needed. They wanted to do both full-chip circuit simulations and EM-IR analysis.

Yao’s group has been a user of Cadence’s Spectre Simulation Platform products, such as the Spectre Accelerated Parallel Simulator (APS). For this 7nm project, they started to use the newer Spectre X Simulator. Circuit designers would choose between five different accuracy modes in the Spectre  Simulator.

Spectre X

The Spectre X Simulator was announced in 2019, and the attraction for Xilinx in using it can be summarized in a few metrics:

  • Scales to use hundreds of Cores
  • More speed and capacity than Spectre APS

In general, Yao reported that the Spectre X Simulator could complete runs up to 10X faster, and for design netlists that were 5X larger than what the Spectre APS tool could handle. The big question with a new simulator is always, how accurate is it compared to my reference?

Benchmark results showed that the Spectre X numbers were quite accurate, within 1% of their reference results. On capacity, they were able to run circuit simulations that had 20 million nodes in the Spectre X Simulator. Circuit designers would choose between five different accuracy modes, all depending on the types of circuits being simulated: Cx, Ax, Mx, Lx, Vx

spectre x min
Source: Cadence

Accuracy vs Speed

For functional verification needs the engineers used the Vx mode, which offered the highest capacity, while being slightly less accurate. On the other extreme, for sensitive circuits like making jitter measurements or doing RF analysis, then the Ax mode was used.

Case Studies

The first case study was for a CLK network circuit, where the input clock is redistributed to all I/O blocks. The Spectre X Simulator had a run time of just 3 hours, 48 minutes, while using 188G of RAM.

  • 107M nodes
  • 58M capacitors
  • 146M resistors
  • 10M active transistors
  • 3X faster than a third-party FastSPICE tool
  • 12X faster than Spectre APS

A second case study showed a wide-band transformer-based VCO. The Spectre X Simulator had a runtime of 2 hours, 39 minutes, while using 33.6G of RAM.

  • 79K nodes
  • 90K capacitors
  • 1.5M resistors
  • 16K transistors
  • 4X faster than Spectre APS (Mx mode)

As an added comparison point, the Ax mode was also run, and it was 2.4X faster than Spectre APS with under a 0.5% difference in accuracy.

Summary

Designing circuits for the 7nm node is a tough job, and the team at Xilinx was quite successful in bringing to market their new ACAP family of chips. The size of running extracted netlists in a circuit simulator is only getting larger with each smaller process node. To get accurate timing, power and EM/IR results requires a greater simulation capacity, and scaling to support faster run times.

Pei’s engineering group at Xilinx was able to use the Spectre X Simulator to meet all of these new challenges, and they even used the Spectre X-RF Option for harmonic balance noise analysis.

Related Blogs

Share this post via:

Comments

2 Replies to “Circuit Simulation Challenges to Design the Xilinx Versal ACAP”

You must register or log in to view/post comments.