Tag: ACAP

Webinar: System Simulation of Versal ACAP Designs (US)

Webinar: System Simulation of Versal ACAP Designs (US)
by Admin on 10-11-2023 at 3:31 pm

LIVE WEBINAR:

System Simulation of Versal ACAP Designs (US)

Louie De Luna, Director of Marketing, Aldec

Thursday, November 16, 2023

11:00 AM – 12:00 PM (PST)

Abstract:

AVersal ACAP, developed by Xilinx/AMD, is a groundbreaking adaptable platform composed of AI Engine (AIE), Processing System (PS), Programmable Logic

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Circuit Simulation Challenges to Design the Xilinx Versal ACAP

Circuit Simulation Challenges to Design the Xilinx Versal ACAP
by Daniel Payne on 06-24-2021 at 10:00 am
Categories: Cadence, EDA
2 Comments

xilinx versal acap min

One of the most unique acronyms that I learned about this past year is ACAP from Xilinx, which stands for Adaptive Compute Acceleration Platform. At the recent Cadence LIVE event, I had the pleasure of watching Pei Yao, a Xilinx senior staff CAD engineer, as she talked about the challenges of getting all the analog and mixed-signals… Read More

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Xilinx Moves from Internal Flow to Commercial Flow for IP Integration

Xilinx Moves from Internal Flow to Commercial Flow for IP Integration
by Daniel Payne on 08-25-2020 at 10:00 am
Categories: EDA, Empyrean, FPGA, Xilinx
1 Comment

Xilinx IP min

I’ll never forget first learning about Xilinx when they got started back in 1984, because the concept of a Field Programmable Gate Array (FPGA) was so simple and elegant, it was rows and columns of logic gates that a designer could program to perform any logic function, then connect that logic to IO pads to drive other chips … Read More