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#56DAC – Panel Discussion: Closing Analog and Mixed-Signal Verification in 5G, HPC and Automotive

#56DAC – Panel Discussion: Closing Analog and Mixed-Signal Verification in 5G, HPC and Automotive
by Daniel Payne on 06-04-2019 at 9:53 am

Monday afternoon at #56DAC I enjoyed attending a luncheon panel discussion from four AMS experts and moderator, Prof. Georges Gielen, KU Leuven. I follow all things SPICE and this seemed like a great place to get a front-row seat about the challenges that only a SPICE circuit simulator can address.  Here’s a brief introduction for the moderator and panelists:

Cadence luncheon, panelists

Georges Gielen, KU Leuven – Moderator
Researching for past 30 years in AMS area.
Functional verification of AMS is through SPICE simulators.

YY Chen, MediaTek
Analog CAD team, packaging.
Creating behavioral models is our most difficult challenge, and we have to work with system guys to create a model. Replacing a schematic netlist with behavioral models is our goal in order to speed up simulation times. System simulation requires behavioral models.

Atul Bhargava, STMicroelectronics
Analog flows, parasitic extraction, reliability.
Diversified chips: uC to automotive, all complex SOC design trends. Reliability needs are an issue. New nodes, parasitics of wires and devices require much more complex modeling. The number of transistors and parasitics is exploding, making it much tougher to simulate. Accuracy and speed are both required. We have three choices: SPICE, FastSPICE, Analog FastSPICE.

Roopashree H M, TI
Analog EDA leader, entire AMS tool flow at TI.
Vertical segments that we serve include : medical, industrial, automotive. Mixed signal verification is an issue, especially as our chips can have both low and high voltage, like 200V, so we need safe operating areas, analog fault coverage for automotive, and reliability of semiconductors over the life of each product.

Vinod Kariat, Cadence
R&D, done P&R, signoff analysis, all circuit simulation R&D.
Visited many customers and found that 80% of compute resources is in Analog Simulation, Verification and Digital Verification. Advanced nodes for smart phones have shown parasitics issues can dominate timing. Power management chips require reliability, aging, and safety issues. Power saving modes are quite complex, with low voltages near threshold, and a huge amount of verification work. We’ve improved circuit simulator capacity and speeds with a new circuit simulator, Spectre X, a generation beyond Spectre APS.


Q: Are commercial tools for SPICE circuit simulation sufficient for today?

Atul – we always need more speed from our SPICE simulators.

Roopashree – it’s a never ending challenge for SPICE simulators. What about using more formal methods for AMS design? TrueSPICE gives us accuracy confidence.

Vinod – today we can simulate millions of devices, 10’s of millions of parasitics. There are not much formal methods applied to AMS yet, but we expect the Universities to lead in this new area. Our Verifier product helps to define a better verification plan for AMS, but still it’s not a formal method, so we’re slowly moving in that direction like the digital tools.

Q: Circuits are becoming more complex, are you keeping up?

Vinod – we’re not falling behind on complexity challenges, but other areas of verification have increased too fast for circuit simulators.

Roopashree – we want to approach analog verification more like digital verification.

Atul –  variability before using just 3 sigma was adequate, but now 5-6 sigma requirements are common in AMS, causing vast simulation increases.

Q: Does ML and AI help simulations?

Atul – we can do 6 sigma simulations today, but it takes too much time. PPM is now becoming a PPB (parts per billion) requirement.

Q: Are we covering reliability well?

YY – there’s not an efficient methodology today for reliability.

Q: Behavioral model creation is a manual process now, do you see any improvements coming?

YY – we’re looking for automation of Behavioral Models, instead of manual checking process now.

Atul – I agree with YY, about 20 years ago TrueSPICE was good enough, then with Spectre X we see speed improvements se we are able to handle 1M elements. We still want behavioral modeling improvements.

Vinod – SPICE speed gains are always welcomed by designers. We want to be ready for new design challenges, so parallel Spectre X was born. The holy grail of automatic behavioral model generation is always just out of reach, and behavioral modeling requires a rare person that knows how to both code and do analog design. Validating Behavioral models also takes massive simulation efforts, especially as the circuit changes then BLM needs calibration again.

Q: Deeper CMOS technology has more complex device behaviors, does that break simulators?

Vinod – we’re still able to model accurately at 5nm and 3nm, so no limits seen on the modeling side.

Q: Testing of AMS parts requires zero defects, how is fault simulation working out?

Roopashree – it’s been a long journey for analog, we aren’t there yet, although we can do fault injection now for analog, so we’re headed the right direction. It’s an exponential problem, but very compute intensive.

Atul – yes, we’re reaching our goals, but the number of simulations is still exploding, so doing digital fault insertion for analog is feasible, but when will we do analog fault injection in analog circuits for effects like resistance bridging?

YY – we’re using Legato for analog fault simulations.

Vinod – we’ve been talking about analog fault simulation for the last 10 years now, and we can do fault injection now for analog. Digital fault simulation has been around since 1970, while analog is still decades behind, it’s still nascent.

Q: Chips are now using a 3D stacked approach, how does that change simulation requirements?

Roopashree – we can simulate multiple chips with different technologies at the same time now. It’s also possible to simulate chip and package together OK.

Vinod – engineers can do full 3D extraction with Clarity using FEM. You really want to do chip simulation with package parasitics included prior to system simulations.

Open Q&A

Q: What is teh highest priority for improving simulations?

Atul – There’s no single dimension answer, because it all depends on your product. For medical it’s accuracy, for industrial it’s different like performance. ADAS products require accuracy. Infotainment is performance.

YY – functional is most important.

Vinod – accuracy is good enough today, so we tend to improve speed first then capacity second.

Roopashree – we want to launch simulations more efficiently and find all of the outliers.

Q: What are you not doing today because of limitations?

Vinod – reliability simulations.

Q: Digital mixed-signal verification has some VIP, but on AMS there are no VIPs. Can analog learn from something like UVM?

Vinod – in general we want digital verification methodologies to be applied in analog, helping us to meet coverage goals.

Roopashree – we should have analog engineers learn from UVM.

Q: Why not do a HW accelerator for SPICE?

Vinod – the digital world has already done that with emulators because it is economical for software bring up. Analog workloads constantly change because the circuit sizes change, so we need to cost effectively run lots of smaller circuits. Custom silicon for SPICE may not make economic sense. We are using 40 core CPUs right now for parallel SPICE. We’re looking at HW ideas.

Atul – we have a large variety of simulations used, small to large, so not sure about HW accelerators.


A very lively panel discussion today from experts at a variety of companies: KU Leuven, Cadence, TI, MediaTek and STMicroelectronics. The need for SPICE circuit simulation has only increased at each smaller node, and the industry appetite for more simulation cycles for designing automotive, 5G and HPC applications ramps ever higher each year. Parallel SPICE circuit simulators like Spectre X directly address the capacity, speed and accuracy demands, so that’s some good news.

Let’s see how our industry addresses analog fault modeling and simulation in the coming year, along with making behavioral modeling more automated.