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September 23, 2021April 14, 2022

The Path to 200 Gbps Serial Links

The Path to 200 Gbps Serial Links
by Kalar Rajendiran on 09-23-2021 at 10:00 am
Categories: Alphawave Semi, IP

Ethernet speed evolution has kept a nice pace over the years even without any competing communications standard. And there are no signs of that slowing down, thanks to innovative companies deploying creative design techniques to keep delivering high-performance SerDes IP solutions. SerDes plays an integral role in implementing highspeed Ethernet connectivity.

The voracious appetite for high-speed data connectivity is driven by applications such as 5G, 4K on-demand video, audio streaming, photo sharing, IoT and AI deep learning. The hyperscale data centers supporting many of these applications and the “enterprise move to the cloud” initiatives play catalyzing roles in driving rapid adoption of the latest SerDes technologies in implementing Ethernet solutions. 112Gbps SerDes milestone was reached just in the recent past enabling easier implementations of 400G and 800G Ethernet connections.

Last month, at the DesignCon 2021 conference, Alphawave IP made a presentation titled “The Path to 200 Gbps Serial Links.” The presentation was authored by Tony Pialis (CEO) and Clint Walker (VP Marketing) and the talk given by Clint. Many of you know and/or have heard of Alphawave IP. They have been making waves recently in the wake of their IPO in a short span of four years from inception of the company. According to Dealogic, this is the largest semiconductor IPO in history.

What you may not know is that Tony is a serial entrepreneur, having founded three successful companies in the highspeed connectivity space. It is hard to believe that we were discussing 5Gbps not that long ago when I first met him and he is talking 224Gbps now. Okay, it was 15 years ago during his Snowbush days when I first met him. When most other solutions at that time were taking the all-analog route, Tony was talking DSP-based implementation. He was and still appears to be a firm believer in the scalability of that approach and the results speak for themselves. One of the many products that Alphawave IP offers is a 112Gbps Long-Reach (LR), low-power, DSP-based Multi-Standard-SerDes.

Knowing Tony, Alphawave IP doesn’t rest on its laurels. Right on the heels of launching their 112Gbps SerDes, they were off to the races, experimenting in their labs to achieve 224Gbps SerDes. The presentation at the DesignCon2021 was about their experimentation, their findings and predictions based on that. This blog will summarize the key points from that presentation.

Industry Adoption of Latest Connectivity Solutions

From a data center perspective, a move toward higher speed Ethernet connectivity promises not only power savings but also area savings thereby increasing interconnect densities. So, the industry is always eager to quickly adopt technologies that will help them move in that direction.

The above figure is loaded with useful information. The middle chart is very interesting to take a closer look. When a 200Gbps SerDes becomes available, 1.6TbE becomes possible. One with an 800GbE connectivity current offering can double their connectivity speed without changing the complexity of their design too much. Alternatively, they can maintain the 800GbE connectivity offering and reduce the complexity of their design. Either way, they get to enjoy the benefits of lower power of the next gen SerDes.

Challenge of Scaling to 224Gbps SerDes

Designs adopted PAM4 signaling to support data rates beyond 25Gb/s. But PAM4 signaling is much more sensitive to noise, reflections, non-linearities and baseline wander. Receiver design is much more complicated. Refer to figure below to see the stringent requirements on signal-to-noise (SNR) ratio and jitter spec to deliver 224Gbps SerDes. In order to drive reasonable channel lengths, insertion losses from packaging, board and cable need to be reduced in half.

Alphawave IP’s Experimentation

This presentation focuses on signal modulation experimentation to determine signaling scheme that will deliver 224Gbps rates. Alphawave IP considered 2-PAM, 4-PAM, 6-PAM, 8-PAM QPSK and 16-QAM modulation schemes for their experimentation. Higher modulation schemes introduce higher bit error rates (BER). In order to reduce BER to an acceptable 10^-6 they had to improve SNR by 1-3dB. They tried advanced DSP detection to leverage Maximum Likelihood Sequence Detectors (MLSD) in achieving 1-3dB improvement in SNR. They were able to improve BER by two orders of magnitude.

After narrowing down their choices to PAM4 and PAM6 modulation schemes, they ran experiments with two different channels per modulation scheme.

As you see in the figure above, both the channels with the PAM6 modulation scheme delivered results that meet or exceed the requirements stated earlier. BER in the 10-6 range (or better) and SNR higher than 20.5. The PAM4 modulation scheme did not deliver.

Alphawave IP’s Findings

Alphawave IP’s conclusion is that PAM6 is a feasible modulation scheme for 224Gbps long-reach electrical transmission for channels used in this study. PAM4 will work for very short reach (VSR), medium reach (MR), chip to chip (C2C) and chip to module (C2M) electrical links. A total link solution that enables PAM4 for long reach channels is preferred.

If the industry as a whole can find a way to make PAM4 possible for a total link solution, that would be a big benefit for everyone involved. This calls for collaboration among different players within the ecosystem. For example, packaging, board and cable vendors working together with the goal of reducing insertion losses to enable longer channels. System vendors working toward reducing channel length requirements.

If the industry collaborative efforts don’t yield a total link solution at PAM4, PAM6 can be used to support channels where insertion loss deteriorates too rapidly.

Summary

If you’re part of the ecosystem involved with designing and deploying high-speed connectivity solutions, you would want to discuss more details with Alphawave IP.

Also Read:

Enabling Next Generation Silicon In Package Products

Alphawave IP is Enabling 224Gbps Serial Links with DSP

CEO Interview: Tony Pialis of Alphawave IP

September 23, 2021April 14, 2022

More Tales from the NoC Trenches

More Tales from the NoC Trenches
by Bernard Murphy on 09-23-2021 at 6:00 am
Categories: AI, Arteris, Automotive, IP

Science texts like to present the evolution of knowledge as step-function transitions, from ignorance to wisdom. We used to think the sun revolved around the earth. Then Galileo appeared, and we instantly realized that the earth revolves around the sun. But reality is always messier, as Galileo understood all too well. The transition from darkness to light is often bumpy. The same can be said for adopting new technologies. There may be mechanical challenges along the way, but the biggest barriers are often our own preconceptions. I talked to William Tseng (AE Manager) and Kurt Shuler (VP Marketing) at Arteris IP to share more tales from the trenches on this learning curve in NoC adoption.

Let’s go for the state-of-the-art solution!

You’re ready to make a major change in implementation architecture, so you might as well go the whole way, right? Read the latest papers, find out where all the excitement is and go for that. No compromises. According to William, this is an especially common viewpoint in research institutes. Those big organizations around the world bridge academia and industry, helping translate research ideas into something closer to real applications.

These outfits are stuffed with intellectual heavyweights, all PhDs and all well connected with counterparts in universities across the world. In their domains, they reign supreme. Not the kind of people with whom you want to get into a technical argument. Except that, like all of us, they sometimes can have a blinkered view of larger needs. Take NoCs as an example. The hot architecture is meshes because that’s what’s taking over new server and AI training SoCs. What an endorsement, right?

The bleeding edge isn’t always the right solution

This is a great direction to go if you’re building Gravitons or TPUs. Lots of uniform processors arrayed inside a mesh. But the great majority of us are building more heterogeneous systems. Containing video pipelines, roots of trust, a variety of IO peripherals, sensor fusion, inference engines, wireless connectivity. A kitchen sink of IP and connectivity needs. As an exercise, you could make that all fit inside a mesh. Distort the mesh here and there to fit larger IPs or make off-grid connections. It’s possible, but you start to wonder if it’s worth the effort. You still must meet PPA goals, and your previous design looks nothing like a mesh.

Which is where those research heavyweights start to come around. For most commercial applications, a more flexible NoC architecture is preferable. Something that can flow between IPs, as you’d expect from a NoC. That will support a mesh where an array solution is what you need but is equally at home and efficient in managing your kitchen sink of IPs and connectivity.

Use cases, architecture, and the interconnect

A challenge for any component vendor is that prospective buyers are happy to talk about the component but see no need to discuss their larger objectives. Why should software architects or product application engineers get involved in the discussion? They’ll reveal secrets the vendor shouldn’t know. Or perhaps sometimes that the integrators themselves don’t know.

William said that a common problem in helping small system teams transition to large systems is understanding how they want to manage traffic on the on-chip network. Designing effective traffic management requires some understanding of use cases. If the integrators are new to NoCs, they’ll have to turn to the NoC experts (here, Arteris IP) in a discussion together with the software and application experts. Which paths will be used most heavily? Do they know which paths must have low latency? Which can afford to be a little slower? System architects know how to answer these questions. Based on which the NoC experts can suggest an architecture for the interconnect. Architects may refine their answers over time, but once the integrators understand the NoC design concepts, they can adapt easily enough.

Coming to terms with safety

Teams with a background in small designs and now on a fast ramp are often inexperienced in all the complexities of meeting safety needs for automotive and other domains. This is another area where a component mindset can get in the way. William tells me what these kinds of integrators are looking for is an assurance that the component will be safe no matter how they use it.

Which, of course, no one can give. That’s why ISO 26262 details concepts like development interface agreements, system elements analyzed out of context and assumptions of use. Those define the boundaries around which the component vendor will provide assurances of safety.

Kurt has told me before that getting past this point takes a discussion (maybe a few). About Arteris IP experience in working with many customers in the field. About their long-standing involvement with the standard and commitment to the spirit and not just the letter of the standard. And about the practicalities of ensuring safety through the value chain, from IP to device, to module to car. Requiring not just good components but also experienced support throughout. Ultimately setting a higher bar for safety compliance than a simple checklist.

Different yes, but also better

Galileo had the harder sales job, but ultimately, he was right. People needed to change their perspectives to understand why his model was better. As they sometimes need to with NoCs. With a different perspective comes a better outcome. You can learn more about Arteris IP solutions HERE.

Also Read:

Smoothing the Path to NoC Adoption

The Zen of Auto Safety – a Path to Enlightenment

IP-XACT Resurgence, Design Enterprise Catching Up

September 22, 2021January 13, 2023

Webinar: PICMG COM-HPC® – New Open Standard for High Performance Compute Modules

Webinar: PICMG COM-HPC® – New Open Standard for High Performance Compute Modules
by Mike Gianfagna on 09-22-2021 at 10:00 am
Categories: Events, Samtec, Semiconductor Services

The subject of this webinar is focused on the new COM-HPC standard from PICMG, a nonprofit consortium of companies and organizations that collaboratively develop open standards for high performance telecommunications, military, industrial, and general-purpose embedded computing applications. A computer-on-module (COM) is a type of single-board computer that is a subtype of an embedded computer system. An extension of the concept of system on chip (SoC) and system in package (SiP), COM lies between a full-up computer and a microcontroller. These systems form a backbone for many embedded applications and the new COM-HPC® standard replaces the popular COM Express® standard, deployed in 2005. Everything is now faster and denser, so this new standard is important. Read on to learn about the new open standard for high performance compute modules.

The webinar is hosted by Mouser Electronics and Samtec. Matt Burns, technical marketing manager at Samtec is the presenter. I’ve known Matt for a long time, and I can tell you he is very knowledgeable about Samtec’s products and their impact on system design. Over the course of the last 20 years Matt has been a leader in design, technical sales and marketing in the telecommunications, medical and electronic components industries. So, what’s important about the new COM-HPC standard and why should you care? The webinar answers these questions with great clarity and depth. Let’s take a look at what you’ll learn if you attend. A replay link is coming.

Client Carrier with COM HPC module for PICMG

Spoiler alert: The demands of PCIe 5.0 drove a lot of this. The infusion of AI into everything has also increased the need for performance. Interoperability is also front-and-center, as is the importance of edge computing. Matt explores all of these system drivers and more during the webinar. The capabilities supported by COM-HPC are discussed in detail, along with the physical channel capabilities offered by Samtec. The webinar will give you a good understanding of the hardware options available from Samtec and how they will help your system design. You can learn more about Samtec through the various posts about them on SemiWiki here.

A comparison of COM-HPC and COM Express is very helpful to understand the relative performance delivered by each of these standards. The various COM-HPC form factors are also reviewed, along with capabilities and potential applications. The COM-HPC form factors reviewed during the webinar include:

Size A
- 95mm x 120mm
Size B
- 120mm x 120mm
Size C
- 160mm x 120mm
Size D
- 160mm x 160mm
Size E
- 200mmx160mm

COM HPC boards

The various client module sizes are reviewed, along with a list of possible applications. These include:

Medical equipment
High end instrumentation
Industrial equipment
Casino gaming equipment
Ruggedized field PCs
Transportation
Defense systems
AI and machine learning
Autonomous vehicles
Medical equipment
Cell tower base stations
Defense systems

Power budgets for various applications are also discussed. Some of the details of Samtec COM-HPC interconnect solutions are reviewed, including:

High-performance, flexible open-pin-field array
High-speed PCIe® 5.0 and 100 Gb Ethernet capable
400 pin BGA mount
4 rows x 100 columns
2 / 2.4 / 2.2 mm row pitch
635 mm pitch
5 mm or 10 mm stack heights
Dimensions: 68.62 mm x 9 mm x stack height
Up to 360 W at 11.4 – 12.6 Volts

Samtec solutions

Details of the signal integrity performance of various Samtec solutions are also discussed, along with detailed performance plots. There is an excellent live Q&A session with the audience following the presentation for about 10 minutes. Overall, you will learn a lot during this webinar that is directly applicable to your next design project. You can access the webinar replay here to learn about the new open standard for high performance compute modules.

Related Blog

September 22, 2021December 6, 2024

Cautions In Using High-NA EUV

Cautions In Using High-NA EUV
by Fred Chen on 09-22-2021 at 6:00 am
Categories: Lithography
1 Comment

High-NA EUV has received a lot of attention ever since Intel put the spotlight on its receiving the first 0.55 NA EUV tool from ASML [1], expected in 2025. EUV itself has numerous issues which have been enumerated by myself and others, most notoriously the stochastic defects issue. There are also a host of issues related to the propagation of the EUV light in 3D through the mask topology, with shadowing being the easiest description of the phenomenon [2]. It has already been disclosed by one EDA vendor, in fact, that EUV is being practiced with multipatterning [3], defeating the purpose for which it was originally intended. So, with the entry of high-NA EUV, the prospect of single patterning EUV makes it a very attractive option. What changes can we expect with a high-NA EUV system compared to the current EUV system?

Improvements with High-NA

The high-NA increases the numerical aperture (NA) from the current value of 0.33 to 0.55. The first benefit is this decreases the minimum optical spot size to 60% of its current value. The nominal value is given by the Rayleigh criterion of 0.61*nominal wavelength(=13.5 nm)/NA, which is 25 nm for 0.33 NA and 15 nm for 0.55 NA. This of course, helps gives a sharper aerial image, i.e., the classically projected image at the focused point in space. In reality, the image is noisier due to the limited number of photons and blurred by electrons and chemical species in the resist.

A second benefit from the high-NA system is the increased demagnification in the Y-direction (from 4X to 8X). This has the effect of reducing the spread of angles. Keeping the original 4X would have resulted in a prohibitive range of angles. This helps reduce the impact of the 3D propagation through the mask mentioned earlier. Furthermore, since the X-demagnification is the same, there is also a reduction in the range of azimuthal rotation of the plane of incidence through the slit. The illumination sine ratio (kx/4)/(ky/8) = 2 kx/ky on the mask is halved to kx/ky on the wafer, whereas for the current imaging systems the same ratio (kx/4)/(ky/4) on the mask is preserved as kx/ky on the wafer. Thus, this improves the illumination consistency through the slit.

Complications/Tradeoffs with High-NA

There are three issues with the move to a higher NA. The first should be well-known to lithographers, since it is the reduced depth of focus [4]. While the 0.33 NA 13.5 nm wavelength gives a depth of focus of 120 nm, increasing the NA to 0.55 reduces the depth of focus to a third of that, 41 nm.

The second issue is a consequence of the 8x Y-demagnification. Since the EUV mask 104 mm x 132 mm field size is not changing, the scanned field on the wafer has to be halved (in Y) from 26 mm x 33 mm to 26 mm x 16.5 mm. If a chip pattern originally took up over half the 26 mm x 33 mm field (as usually the case, even as 3 x 3 dies, for example), it would be chopped midway, leading to the need to stitch the two parts together through the exposure of two masks. Hence, double exposure patterning may creep in, spoiling the single patterning scenario.

The third issue is definitely a gotcha, since it was supposed to have been avoided at all costs in previous lithography system designs. The use of larger mirrors in the high-NA EUV system has led to unavoidable obscuration, where one mirror cannot avoiding blocking another. This has fundamental optical consequences, particularly reduction of modulation at lower spatial frequencies [5]. In some cases, the effects can be very drastic. In the example of a staggered 40 nm x 40 nm array below, the (1,1) diffraction orders is obstructed by the central obscuration in the pupil of the 0.55 NA system.

In this example, it would lead to a doubling of the spatial frequency in the x and y directions, which is a basic imaging error. Since a portion of the pupil is covered by forbidden illumination zones (shown in red), this is difficult to integrate with other patterns which normally require more flexible illumination. This is something the high-NA EUV user has to be especially aware of.

No, stochastics will not go away

The use of higher NA reduces the spot size, and hence, the image pixel size is also effectively reduced. We also expect the resist blur to be reduced in order to take advantage of higher resolution. Hence, at the same dose and k1 (feature size normalized to wavelength/NA), the number of photons in the same number of edge pixels will continue to decrease. This means the stochastic issues of EUV imaging will persist at the feature edge.

References

[1] https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros

[2] A. Erdmann et al., “3D mask effects in high NA EUV imaging,” Proc. SPIE 10957, 109570Z (2019).

[3] https://www.ednasia.com/multi-patterning-strategies-for-navigating-the-sub-5-nm-frontier-part-3/

[4] B. J. Lin, “The k3 coefficient in nonparaxial l/NA scaling equations for resolution, depth of focus, and immersion lithography” J. Micro/Nanolith. MEMS MOEMS 1(1) 7–12 (April 2002).

[5] S. T. Yang et al., “Effect of central obscuration on image formation in projection lithography,” Proc. SPIE 1264, 477 (1990).

This article originally appeared in LinkedIn Pulse: Cautions in Using High-NA EUV

Arm Shifts Up With SOAFEE

Arm Shifts Up With SOAFEE
by Bernard Murphy on 09-21-2021 at 6:00 am
Categories: Arm, Automotive, IP

We’re always hearing about shift-left, advances enabling system designers to start various aspects of their development and validation earlier. In support of this goal for automotive developers, Arm recently announced their Scalable Open Architecture for Embedded Edge (SOAFEE). SOAFEE is a software platform (with reference hardware) designed to enable shift left through cloud-native software development in the new and evolving automotive world. Supporting the likes of Volkswagen who have a publicly stated goal to develop 60% of their software in-house by 2025.

Motivation

It’s no secret that automotive OEMs and others are exploring new ways to deliver and monetize mobility, as EV opportunities expand, dealership models are in question, Mobility as a Service is a hot topic and ADAS/autonomy continues to advance. Cloud service providers and others also see opportunities to claim a part of the action, seeing a move away from traditional supply chains to more collaborative development and support. Several invited Arm to drive an open architecture standard to rationalize a foundation for this software development. The standard, represented by a SIG, now includes AWS, Continental, Cariad (a VW Group company), Woven Planet (a subsidiary of Toyota), RedHat and GreenHills among others.

Why do I say Arm has shifted up to this objective? Because they are doing something they have always done well (now stretching further), which I’m now starting to see among a handful of other tech companies. Shifting up from a space in which they’ve proven themselves, to bridge a gap to the system-level needs of their ultimate system customers.

The SOAFEE Framework

SOAFEE is about enabling the software defined future of automotive. Enabling functions and capabilities through software control. Abstracting the underlying hardware to ensure portability, while preserving awareness of hardware capabilities and constraints. Putting this in place in the cloud enables OEMs to start development sooner. With that cloud-native starting point they can easily update and manage software throughout the product life cycle. Experienced cloud-based developers and app builders will also be able to contribute. All can leverage cloud-based development and deployment techniques.

Cloud-based developers still need to model realistic real-time and power behaviors. To that end, Arm has partnered with ADLINK to provide two hardware reference platforms. A 32-core Ampere Altra SoC for lab development/prototyping. And an 80-core Ampere Altra SoC in a ruggedized box for in-vehicle testing. (This box also hosts an on-board ASIL-D safety MCU.)

The software stack mirrors between the in-vehicle platform and the cloud platform. To ensure that what you develop early in the cloud should just drop into the vehicle. The same should be true for updates. Hardware and software stacks are built on top of Project Cassini (another open standard from Arm). Two major components here of interest to hardware developers are the SystemReady standard, covering a range of system compliance topics, most notably in-system PCIe compliance. And PSA-certified, covering security requirements.

Availability

The SOAFEE reference software stack is already available. The reference hardware is available for pre-order now from ADLINK.

I’m impressed. In a diverse ecosystem like the one already growing around evolving automotive needs, someone needed to step up. To ensure a common based reference for all those potential developers. Arm not only stepped up but also shifted up. To build that bridge from their world to the world in which auto solution builders want to work. You can read the press release HERE.

September 20, 2021April 13, 2022

WEBINAR: SkillCAD now supports advanced nodes!

WEBINAR: SkillCAD now supports advanced nodes!
by Daniel Nenni on 09-20-2021 at 10:00 am
Categories: EDA, Events, SkillCAD
1 Comment

Originally containing a handful of commands to help with common layout tasks, SkillCAD has evolved into the industry standard for analog, RF and mixed signal design for customers using Cadence Virtuoso. With over 85 customers worldwide and over 120 functions including the powerful, patented V-editor, metal routing and pin placement tools, SkillCAD’s offering is proven to significantly improve layout design team productivity.

Today, design teams face a new challenge as the adoption of leading-edge process nodes is accelerating faster than previously anticipated due to substantial power, performance and density improvements. The downside is that design teams are now faced with the exponential increase in design rules and time-consuming iterations of layout to achieve a “clean” design. Project schedules suffer as layout times increase to 2X or 3X what they were in previous nodes.

The SkillCAD strength is the ability to quickly develop new layout commands that significantly improve design team productivity by automating repetitive tasks which also reduces design errors. SkillCAD develops these new layout commands by working closely with customers who specify the functionality needed for their designs. Once the new command is developed and tested, SkillCAD then offers these new commands to all customers to be used inside the Cadence Virtuoso environment.

Today SkillCAD has over 30 commands that work with 7nm, 5nm, and 3nm. The new coloring functions are compatible with the Virtuoso coloring method, but also supports in-house coloring methods that allow designers to use a different layer purpose for different colors to minimize mouse clicks while significantly reducing the time in color editing. The new SkillCAD routing functions intelligently take advantage of the strict design rules in advanced nodes, consolidating steps into a single mouse click that can significantly increase wiring speed. SkillCAD will continue to add functionality working closely with customers to develop new commands specific to supporting advanced nodes and unique design styles.

WEBINAR REPLAY: Automating FinFET Layout

Abstract: To address the layout challenges in advanced node designs, SkillCAD has released a new module to handle the complexities associated with color-aware physical design and routing to improve the productivity of your layout team.

The new functionality offers a variety of layout capabilities for coloring and routing. The coloring functions are compatible with the Virtuoso coloring method, but also supports in-house coloring methods that allow designers to use different layer purpose for different colors to minimize mouse clicks while significantly reducing the time in color editing.

Our new routing functions intelligently take advantage of the strict design rules in advanced nodes consolidating steps into a single mouse click that can significantly increase wiring speed. SkillCAD will continue to add functionality to this new module as we work closely with our customers to develop new commands specific to advanced nodes.

Speaker: Pengwei Qian (SkillCAD)

Speaker Bio: Pengwei Qian is the founder and CEO of SkillCAD, a grassroots EDA company that has 80+ companies using IC (LAS) worldwide. Pengwei has a Bachelor’s degree in Physics and a Masters in Material Science from Fudan University and a Masters in Electronic Engineering from National University of Singapore. He started as an IC designer and now has more than 20 years of experience in EDA.

WEBINAR REPLAY: Automating FinFET Layout

About SkillCAD
Founded in 2007 to enhance productivity to Cadence Virtuoso layout design flow. Cadence Virtuoso + SkillCad have become the industry standard layout environment for full custom analog, RF, and mixed-signal designs. Over 80% of the major analog and mixed signal (AMS) companies use SkillCad. SkillCad seamlessly integrates with Cadence Virtuoso Layout L, XL and GXL and supports IC5, IC6, IC12, IC18. SkillCad has been a Cadence Connection Partner since 2008.

Also Read:

Webinar: Increase Layout Team Productivity with SkillCAD

SkillCAD Adds Powerful Editing Commands to Virtuoso

SkillCAD Layout Automation Suite has Over 120 Commands Backed by 60 Customers

September 20, 2021August 22, 2024

The GlobalFoundries IPO March Continues

The GlobalFoundries IPO March Continues
by Daniel Nenni on 09-20-2021 at 6:00 am
Categories: Events, Foundries, GlobalFoundries
3 Comments

The GF Technology Summit was last week. It was virtual again this year but with a different format. It was a mix of live and recorded events which did include some cringe worthy moments but all-in-all it was well worth my time.

One of the biggest changes you will notice is the messaging. GF is no longer down in the technology trenches talking to chip designers. Instead GF is talking directly to systems companies about solutions and more importantly highlighting the pure-play foundry value proposition to Wall Street. And given the current semiconductor climate, Wall Street is listening.

The big questions is: Will GF go IPO or be acquired next year? Those two are not mutually exclusive but, in my opinion, they should be acquired. Rather than pouring billions of dollars into an ecosystem and spending years upon years earning customer trust, Intel could hyperscale their foundry efforts in buying GF. And of course, Samsung could make a big defensive move and acquire GF to expand their foundry offerings and customer base. Either way it needs to happen. A pure-play foundry must continue the march down the process node roadmap otherwise it will fade into the technology sunset.

I enjoyed watching GF CEO Tom Caulfield. I do know Tom and hold him in the highest regards. He is a very engaging speaker and a true semiconductor professional. I credit Tom with the great GF pivot of 2018 and I think the GF exit (IPO or acquisition) will be one for the history books, absolutely.

You can see Tom on CNN here:

https://www.cnn.com/videos/business/2021/07/21/globalfoundries-ceo-chip-shortage-semiconductors.cnnbusiness

COVID really has been a blessing and a curse to the semiconductor industry. The world now knows the importance of semiconductors and electronics to modern life. We read about it everyday now. Unfortunately, the disruption to the supply chain is causing a bit of a panic. This of course is not just a semiconductor problem, supply chains across many industries are being disrupted.

I had predicted that the semiconductor supply chain issues would ease this year but clearly that will not be the case. COVID cases are again spiking around the world and may continue for months to come.

Parts of the semiconductor supply chain are doing well. TSMC for example. Taiwan has contained the COVID problem and TSMC continues to grow double digits. And given the hefty CAPEX of TSMC, Samsung, Intel and GF for 2021 and beyond I seriously doubt there will be a wafer shortage anytime soon.

The foundry business model is fairly simple. When a chip design is started a customer commits to a foundry and downloads a PDK (process design kit). A multi year wafer agreement follows and for big customers like Apple, AMD, Nvidia, and QCOM these are sizable agreements. A foundry then builds capacity to satisfy the wafer agreements and all is well assuming the foundry can yield the process in a timely manner. Remember, it takes less time to build a fab than it does to design a CPU, GPU, or SoC so do the math here.

Semiconductor shortages will come when a foundry customer requires more wafers than expected which is what happened with COVID. In fact, some companies paused wafer orders at the beginning of COVID (Automotive) and now are experiencing shortages of their own design.

According to Malcolm Penn of Future Horizons, and he would know, there have been 14 semiconductor shortage (black swan) events in the last 50 years. The one I remember best is the Dot Com boom and bust of 2000. COVID of course is the blackest of swan events (my opinion). Either way, what does not kill us makes us stronger, absolutely.

Also Read:

Magnetic Immunity for Embedded Magnetoresistive RAM (eMRAM)

GloFo inside Intel? Foundry Foothold and Fixerupper- Good Synergies

Silicon Photonics Solutions Address Bandwidth, Reach, and Power Challenges

September 19, 2021September 19, 2021

LiDAR and the End of the Musk Marketing Masque

LiDAR and the End of the Musk Marketing Masque
by Roger C. Lanctot on 09-19-2021 at 6:00 am
Categories: Automotive
4 Comments

One of the key differentiating characteristics of companies working on autonomous vehicles is the willingness to explain or disclose the manner in which this technology works. Tesla and Mobileye have been standouts in the explainer category. Companies like Waymo and Cruise have been less distinguished.

Tesla, though, has weaponized its disclosure process. Company CEO Elon Musk has routinely taken the microphone or the stage to denounce LiDAR technology as unnecessary to the task of automated driving.

Musk’s approach is not unlike the FUD (fear, uncertainty, and doubt) sales tactics reportedly used by IBM sales personnel to discourage potential buyers of competing Amdahl computers. In his own way, Musk has done his best to downplay or dismiss the importance of LiDAR for ranging, object detection, speed, and heading particularly in occluded driving circumstances that tend to render cameras useless.

The IAA Mobility auto show in Munich last week marked an important turning point in un-masking Musk for his deceptive messaging. Mobileye unveiled its Moovit-Sixt robotaxi on the show floor liberally dimpled with short- and long-range LiDAR sensors. Similarly, at a facility outside the IAA event, Argo showed a Volkswagen van equipped with multiple LiDARs.

By the time of the IAA event, leading LiDAR provider Luminar could already point to a range of vehicle partners including Pony.ai, Volvo, Audi, Toyota, Airbus, and even Mobileye. The race is clearly on to lock up these relationships with General Motors announcing post-IAA its plans to put Cepton LiDAR technology to work on its vehicles. IAA was also a coming out event for Lumotive, the latest solid state LiDAR supplier to emerge in the market with substantial financial backing.

The bottom line is that Tesla’s Musk determinedly misled the industry no doubt with the intention of driving down the value of companies developing LiDAR in hopes of saving himself some money in the long run. In the process, his cynical strategy undermined his own company’s prospects and credibility as LiDAR-less Tesla’s continued to crash into parked police vehicles on highways, and the National Highway Traffic Safety Administration was finally forced to initiate an investigation into multiple such crashes.

There is no longer any doubt in anyone’s mind working on autonomous vehicles. More sensors are needed – the greater the number and variety, the better. Musk’s most recent musings that radar is yet another candidate for removal from Tesla vehicles aspiring to automated driving is yet further evidence that he’d rather save dollars than lives.

Musk’s rival at Mobileye, CEO Amnon Shashua – a one-time camera-only devotee – has clearly crossed over into the multi-sensor realm. His robotaxi demonstrations in New York City and Munich have arrived equipped with LiDAR technology.

As a final note, it is worthy of admiration that both Tesla and Musk and Mobileye and Shashua have been willing to explain their strategies and technical approaches to automated driving. It is clear that regulatory authorities will ultimately require that the creators of these systems are able to explain the decision-making behind the operation of their systems. Regulators are not likely to be as easily gulled as competitors, investors, or the general public that de-sensored approaches to automated driving are superior to an approach adopting a more complete sensor portfolio.

It’s one thing for Musk to leave sensors out of the mix in order to hit a more mass market price point for Tesla vehicles equipped with Autopilot. It’s quite something else to suggest this is the preferred configuration. The masquerade is over.

Podcast EP38: Semianalysis on Intel GF TSMC and the Foundry Business

Podcast EP38: Semianalysis on Intel GF TSMC and the Foundry Business
by Daniel Nenni on 09-17-2021 at 10:00 am
4 Comments

Dan is joined by Dylan Patel of Semianalysis.com covering Intel, GF, TSMC, the semiconductor shortage and more. This is a candid discussion between analysts on current semiconductor events.

https://semianalysis.com/

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

September 17, 2021January 27, 2022

CEO Interview: Gireesh Rajendran CEO of Steradian Semiconductors

CEO Interview: Gireesh Rajendran CEO of Steradian Semiconductors
by Daniel Nenni on 09-17-2021 at 6:00 am
Categories: Automotive, CEO Interviews

Gireesh Rajendran is a 2010 MIT TR35 winner from India. He holds 44 issued US patents in RF products and circuit techniques and co-authored 3 ISSCC papers. He completed his B Tech in Electronics from College of Engineering, Trivandrum, India in 2000 and joined Texas Instruments. During his 13 years tenure in TI, he architected and designed several radio products including the 1^st integrated low noise GPS receiver. Gireesh was also instrumental in creating the WLAN product family, WiLink-8 of Texas Instruments with Integrated abg/n Power Amplifier and switch. From 2013 onwards, Gireesh Rajendran was with Qualcomm as the Chip Lead for the mass market LTE-A transceiver used with Snapdragon 6xx and 4xx chipset family. He has defined and executed products which have sold over a billion units.

Please tell us about Steradian Semiconductors and its product offering.

Steradian is a product based vertically integrated company focusing on 4D Imaging Radars. The product encompasses a state-of-the-art Transceiver with FMCW modulation capability in TSMC 28nm CMOS process and a proprietary radar signal processing software stack to generate readily integrable point cloud and tracked objects for sensor fusion.

Steradian has developed the World’s most compact 28nm CMOS Milli-meter wave Imaging Radar chips (SVR4410 and SVR4414) to power their 4D Sensors. The Milli-meter wave antenna and radar processing software from Steradian, when combined with this radar IC enables a complete high performance imaging radar solution. Applications for our products are in Automotive and Industrial sensing, while the radar semiconductor can also be used for Drones and Surveillance.

The Imaging Radar module from Steradian is an all-integrated unit which is used for applications like Traffic monitoring and enforcement to help save lives on the road. Precision parking or smart docking in ports and airports that hitherto required manual guidance can now be automated using our Imaging Radar, thereby improving parking efficiency at a lower cost. Consumer applications like Gesture recognition bring the power of Radar to consumer products as well.

Steradian has filed 14 patents (9 granted) covering various aspects of this product. The company has grown steadily and significantly over the last few years. With its strong team of more than 30 Engineers, Steradian is bracing to support customers for volume production now.

What makes Steradian products unique?

Being a vertically integrated Company, Steradian has a focus on improving the product technology as well as the end application. This helps the customer to keep a view of the entire solution. Steradian Imaging Radar solution has better performance (link budget and noise) and lower power consumption as compared to competition. The enhancements in FMCW techniques through fast-chirping, high sampling data converters, high speed data communications channels (14.4Gbps per chip) have brought in unprecedented specification changes to the conventional Radar. Steradian’s 1-degree angular resolution is validated by customers as the USP of our solution. The improvements in angular and range resolution enable a much denser point cloud output from the sensor. This enables the Radar sensor to migrate from a warning-only sensor to a 4D Imaging Radar which provides information about the size/shape of the objects around the sensor. The proprietary signal processing enables a real-time reconstruction of the surrounding, paving a path for higher levels of autonomy. The precise size, shape of objects as reconstructed through the Imaging radar helps alleviate on-field false alarm challenges such as – a soda can on-road causing the vehicle to stop, whilst not compromising on vulnerable road user (VRU) detection, and putting safety at the centre of the solution. The high elevation resolution allows detection of bridges, vehicle-under-the-bridge scenario and manholes that is not possible with a conventional radar. The high dynamic range of the Radar Front-end and the software stack allows detection of VRU by-the-side of heavy metallic objects (like trucks, fences, and grills) and urban driving scenarios. The commonly faced issues with conventional Radars like metal poles on the road swamping the entire scene are issues of the past now with high dynamic range Steradian Imaging Radar.

How can Steradian help AV/ADAS pursuit?

Reliability and Safety are the heart of Automotive world. While keeping the reliability of conventional radars intact and adding the new dimensions of high-resolution point cloud, Steradian has brought the Radar sensors back to the focus and delivered on “Enhancing vision through Imaging Radar” for AV/ADAS pursuit.

With its high fidelity and near-zero false alarm rates, the Imaging Radar solution is suitable for sensor fusion suites required for higher levels of autonomy. The high-density point cloud provides easy handle for full-stack players to enhance the sensor fusion outputs with an all-weather reliable sensor. The strategic partners ecosystem with established companies in Automotive sector helps Steradian to design and manufacture to the required safety standard.

To bring the technology to a commercially acceptable point, Steradian innovated on the silicon design. Multiple patents on the Radar Front End architecture helped achieve a solution that is scalable across various levels of autonomy. The same platform can be used to design a high-resolution point cloud Imaging Radar for higher levels of autonomy or an economical smart sensor application. The Radar Front End is really processor agnostic. Steradian’s Radar signal processing software stack is conducive to such requirements. This has been a long-standing issue for the full-stack and OEMs – the ability to change the hardware vs software partition and use the available compute in a flexible manner across the Edge and Central processing. Steradian is supporting a 14.4Gbps high speed data link per IC to interface with the available processors.

What do you mean when you say Steradian Radar IC is processor agnostic?

Our radar signal processing software stack is architected to make use of the available compute platform in the best possible manner, in terms of frames-per-second (fps) and power consumption. The conventional techniques of MIMO Radars (including 4D FFT) require several TFLOPS and are quite impractical with commercially viable off the shelf processors for achieving 1 degree and better angular resolution.

Steradian Radar Signal processing provides an elegant, scalable solution to this problem with proprietary techniques. Our patented techniques enable the use of available GPU or DSP platforms (off-the-shelf) for Imaging Radar application while providing >10K points in a single frame. This enables true elevation, size/shape of the objects in a real-time with low false alarm rates. The algorithms are tightly knit with the on-PCB antenna arrangement (microstrip) and together deliver the best trade-off for hardware and software at a viable commercial point.

This architecture also opens newer possibilities in the data processing engine following the point cloud generation. For some applications, the system demands the point cloud to be clustered, tracked, bifurcate static and dynamic objects and even classify the objects. All these requirements are handled much better by the open-processor approach that we have adopted. Customers are much free to adopt available processors and run the SW stack for various approaches to sensor fusion. Also, this approach can give impetus to the transition of automotive radar sensors to newer high data rates architectures (like A-Phy).

Which markets is Steradian targeting?

In the automotive space, Steradian is conducting trails with Tier1’s/ OEM’s for their next generation platform. Qualification and volume ramp up is expected to be beyond 2023.

Our Solution is finding swift adoption in Industrial sensing and Road-safety applications as well. With its ability to isolate closely spaced objects, precise speed, and position detection our Imaging Radar is a suitable sensor for precision parking and Traffic monitoring/enforcement applications. With the migration from 24GHz to 77GHz mandated across the globe, demand for our solution is on the rise. With the rise in contactless applications and privacy concerns with Camera based solutions, the world is embracing Radar technology. More than a million lives are lost on the road due to traffic accidents and a vast majority of them can be attributed to human error. Smart traffic monitoring and enforcement systems can help create safer roads and reduce traffic congestion. Worldwide, under smart city projects, Radars alongside Cameras are providing effective measures to streamline the traffic and thereby saving productive hours. Steradian is ramping up production of radars for these applications.

Final thoughts on the role of Imaging Radars in fully Autonomous vehicles?

The recent announcements from full-stack players and OEMs validate the fact that conventional Radars are not suitable for higher levels of autonomy. The false alarms, ghost objects and missing dimensions in the conventional Radars have been constant pain-points. Imaging Radars are quickly evolving to demonstrate an all-weather, real-time reconstruction of the world around us at a much lower cost point. The road to fully autonomous vehicles might be long but there are no shortcuts for safety and reliability. The post Covid world will prefer contactless technologies. The advancements in Drones, Robots will require sensors that they can rely on to provide high resolution reconstruction of the surroundings under all weather and light conditions. Imaging Radars are placed right to take this spot.

Steradian Semi

Also Read:

CEO Interview: Tim Ramsdale of Agile Analog

CEO Interview: Veerbhan Kheterpal of Quadric.io

CEO Interview: Pete Rodriguez of Silicon Catalyst