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CEO Interview: Tim Ramsdale of Agile Analog

CEO Interview: Tim Ramsdale of Agile Analog
by Daniel Nenni on 09-10-2021 at 6:00 am

Tim Ramsdale Agile Analog 1Tim joined Agile Analog shortly after its formation in 2017, alongside Founder, Michael Hulse, with a mission to change the way Analog IP was designed and delivered. Before joining Agile Analog as CEO, Tim served as General Manager, Imaging and Vision at Arm.  He has experience of delivering products in wireless, consumer, infrastructure and automotive spaces, including to ISO 26262 standards, and a broad knowledge of IC design from physical implementation, analog and digital design up to software, OS and applications.

Tim’s prior roles include VP Engineering for Multimedia Products at Arm, and VP Engineering at Broadcom, where he ran teams of up to 750 engineers over 14 sites, developing highly integrated mixed signal SoCs and application processors for cellular and consumer applications.

Agile Analog is an Analog IP provider, headquartered in Cambridge, UK but with team-members in Switzerland, Spain, Taiwan, California, Edinburgh and Poland. We’ve recently closed a $19m funding round with VCs including OMERS Ventures, Delin Ventures, MMC Ventures and FirstMinute Capital, allowing us to scale the team significantly and broaden our IP offering substantially.

What’s the story behind Agile Analog?

The concept of Agile Analog came from the frustration at the way Analog IP is designed and delivered today – which is broadly similar to the way it was designed 40 years ago! The tools are better, and the compute capabilities and models have improved, but we’ve never had the step change in efficiency gain that digital design has had with firstly synthesis, and then HLS.

Agile Analog set out to change this – to bring AI to bear on a challenge that has often seemed like a ‘black art’ – to be able to design, verify and ship analog IP on any process node automatically.  Having built a team comprising both expert analog engineers, with experience in audio, SERDES, power management, RF and more – working in partnership with a software team with experience in security, data management, scalable computing and media delivery we set out to address this.

The result is COMPOSA – our **configurable, multi-process analog IP platform**. This methodology allows us to take requirements from customers, and quickly turn around designs on their specific silicon process – allowing us to optimise and refine the design to their needs, and ship them a high quality, customised, fully verified design in the time it usually takes to buy standard off-the-shelf IP!

Why are you looking at Analog IP?

Analog IP is critical to every chip that is built – and often shapes foundry choices simply due to the lack of IP availability on some foundry nodes. With the step changes in efficiency we see in the digital flow, the bottleneck for companies building chips becomes the analog components – and either these are left off-chip, which increases cost and power, or drive inefficient implementations, using older processes with great IP availability.

Analog IP development is the last glaring challenge in the IC development process, and we have driven a fundamental new methodology to address it, and are able to transform not only the way people design and develop chips, but also the level of integration they can aspire to.

Analog IP is not just critical to every device – forming the building blocks behind power management, interfacing, SERDES, communications and clocking, but we are seeing innovation in analog circuits delivering significant power benefits particularly for machine learning and audio applications.

As we move to ever deeper integration and intelligence in devices, analog circuits are crucial to every device we ship.

What’s different about Agile Analog?

Thanks to our unique COMPOSA methodology, we are able to generate the IP you want, and you aren’t forced to make compromises on power/performance/area based on the limited IP products that are available to you. We can generate IP which includes the features you need, optimised to suit your application, and compatible with your choice of  [Foundry Process](https://www.agileanalog.com/technical-information/supported-foundries) . And it meets your time-to-market requirements: a typical customer goes from final IP specification to fab-ready IP in as little as four weeks.

In addition, if you requirements change, we can change too – we can deliver IP that has changed specifications, floorplans, or is on a completely different process node just as easily – meaning you can make decisions later, allowing you to make a more optimised product.

Finally – our methodology is completely scalable, which allows us to configure and customise complete IP subsystems for our customers. This allows relatively complex mixed-signal configurations to be specified and designed, customised for specific applications. This can be a decentralised PVT sensor allowing cross-device parameter mapping, a sensor front-end for signal monitoring, an IoT subsystem for control and power management, or a mixed-chemistry battery charger. These can be specified, designed and delivered as a single macro, allowing customers to choose their requirements and performance level.

Tell me more about the security products you’re offering?

We’ve seen a huge demand for our security products – essentially they protect against side-channel and physical attacks. Many people underestimate this as a threat – but there were a number of physical attacks demonstrated at DEFCON this year. Read our blog post here https://www.linkedin.com/posts/agile-analog_defcon29-activity-6834130480833585152-6Ept for more details.

The challenge with digital logic is that it works really well within the operating regime it is designed to work in – so usually +-10% voltage, and -40 to 125C, and the frequency that it was designed for. Outside this range, the behaviour is unexpected – and hackers can use this to their advantage, allowing them to get the device into debug modes and extracting secret data, or re-configuring the device to leak data.

There have been some very public hacks of recent, that show just how significant these attacks are – and we’ve seen location tags, safes, crypto wallets and other devices all attacked in this way.

Agile Analog offers a suite of IP to detect these sort of attacks and allow the system to reject the attack, or delete it’s keys. Our voltage, clock glitch detectors and temperature sensor IP all work in conjunction to detect glitches as small as 2ns – thus protecting secret information and not leaving it open to hacking.  Contact us to find out more, or stay tuned for a webinar on this on SemiWiki!

Who can Agile Analog help?

If you are building an SoC, thinking of building an SoC, or have a portfolio of IP that you need to acquire for an upcoming tapeout, then we can help! We have a skilled team of system engineers that can help you specify your IP to align with the requirements of your application.

Quite often, companies looking at building SOCs don’t include the analog components in their chip specifications – a recent teardown showed that through analog integration we could save 16 external components, and over $2 of BOM (based on 500k/mo quantities) through analog integration alone – and this would also represent a very significant power saving.  We’d be happy to run you through the analysis!

We are also scaling as a company, hiring the best analog and software talent available. If you’re interested in being part of the team, please let us know!

Who should I contact to find out more?

You can contact our Chief Commercial Officer John Hartley, – john.hartley@agileanalog.com. Equally, if you’re interested in job opportunities, contact us at careers@agileanalog.com, or if you are interested in our IP offering, email sales@agileanalog.com. Our website is full of information, including our product roadmap available here: [Roadmap | Agile Analog](https://www.agileanalog.com/technical-information/roadmap)

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