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According to the ESD Alliance, the single biggest revenue category in our industry is for semiconductor IP, so the concept of IP reuse is firmly established as a way to get complex products to market more quickly and reducing risk. On the flip side, with hundreds or even thousands of IP blocks in a complex SoC, how does a team, division or corporation know where all of their commercial and internal IP is being used, and what versions should be used? This brings up the whole topic of digital design management.
I did visit Cliosoft at DAC in San Francisco back in December and blogged about it, so I have been familiar with their general approach to digital design management. Recently I viewed their latest webinar on demand, IP-based Digital Design Management that Goes Beyond the Basics.
If you’re new to the concepts of digital design management, then the first section of the webinar is a great place to learn about how files are managed, versioning control and labeling releases. The digital design flow has many steps, EDA tools, IP blocks, and a variety of engineers with specific duties, so orchestrating this complex process requires a more structured approach.
Digital Design Flow and Personas
In the webinar you will learn how each of the personas on your team will use a methodology to handle the IP Bill of Materials (BOM). specifications, memory maps, documentation, forums and information sharing. Since IP reuse is a major tenet, you need to have a way to quickly search and find the exact IP required for new projects. Having both internal IP and commercial IP in a catalog makes the search more efficient at the start of a new project.
Working across geographies is important, especially in larger companies, so you’ll need a way to define where each part of an SoC is going to be defined and managed. Knowing the bug fix history for each IP block is essential to getting the correct behavior when using an IP instance. Having two versions of the same IP block should be quickly flagged, because in most cases you really want a single version for each IP on the same SoC.
The tasks of verification engineers are discussed, and tips on how to minimize the storage of EDA tool results presented.
Controlling who has access to all of the IP and at what levels (read, write, geography) was presented for enforcing methodology and meeting legal requirements. Automotive (ISO 26262), defense and aerospace design teams need to know exactly where each IP block has been used for ITAR (International Traffic in Arms Regulations) compliance.
They even included a checklist for teams that are considering which digital design management system to use for their complex projects, that way you know what to look for during an evaluation to compare different vendor approaches.
Summary
Cliosoft has a long history in supporting digital design management requirements with tools and a methodology to help ensure compliance and receive automation benefits. IP reuse is the leading methodology for SoC projects today, so having a way to use IP more effectively is a competitive advantage for systems companies.
Artosyn Microelectronics, a leading provider of AI SoCs for drones and other sophisticated applications finds itself at the intersection of hardware architecture and software development. “Our customers are advancing the state of AI programming every day,” said Shen Sha, Senior R&D Manager of Artosyn’s AI Chip Department. “They need early access to the hardware to develop their software. It’s imperative.”
Since 2015, Artosyn has specialized in Image Signal Processors (ISPs) and Neural Processing Units (NPUs), highly advanced ASIC devices that must meet the demanding requirements of low-power and high-performance. These systems represent the most advanced generation of controllers today, employing artificial intelligence for such tasks as object detection, object classification, and object tracking. Artosyn’s chips are at the heart of the latest generation of UAVs (drones), as well as being used in smart surveillance systems, robots, autonomous vehicles, and more.
These are designs of enormous size and complexity, and verifying their correct operation presents its own challenges. “We’ve used many of S2C’s FPGA development systems including their single and dual Prodigy VU440 systems,” explains Sha. “We were able to successfully complete the validation of several complex chips in the hundred-million gate range quickly and efficiently.”
But validating hardware still leaves millions of lines of code to test and verify. As a company dedicated to the customer experience, Artosyn looks for creative ways to help: “In some cases we’ve used the large capacity FPGA-based systems from S2C to directly built a prototype for the customer’s evaluation,” said Sha. “This really accelerates their software development process.”
Sharing the power of S2C’s Prodigy VU440 enabled both companies to leverage a unique form of cooperation – Artosyn was able to swiftly validate their 100-million gate design, and their customer gained access to the hardware critical to furthering their development schedule. Moreover, Artosyn benefits from additional insight by working so closely with their customer; knowledge that helps drive improvements in their own designs. It’s a win for both firms.
S2C specializes in providing leading-edge prototyping platforms for a broad range of design sizes and applications. Built around the world’s largest and fastest FPGAs – such as the Xilinx UltraScale+ VU19P, and the Intel Stratix 10 – S2C’s Prodigy series can scale up to accommodate the largest designs in the hyperscale class. With a rich library of memories, daughter cards, and interface modules, Prodigy systems can be quickly adapted and configured for any purpose. If you’re facing the challenge of large-scale design validation, let us help. Together, we can find a win for you too.
About Artosyn
Artosyn Microelectronics is the leading embedded AI SoC supplier. The application of their chips covers the market such as drones, robots, smart surveillance, and more. Artosyn is known for its solid experience in wireless communication, computer vision and deep learning
About S2C
S2C . is a global leader of FPGA prototyping solutions for today’s innovative SoC/ASIC designs. S2C has been successfully delivering rapid SoC prototyping solutions since 2003. With over 500 customers and more than 3,000 systems installed, our highly qualified engineering team and customer-centric sales team understands our users’ SoC development needs. S2C has offices and sales representatives in the US, Europe, Israel, mainland China, Hong Kong, Korea, Japan, and Taiwan.
I viewed a recent webinar from Paul Clewes of Pulsic, and the topic was Balancing Analog Layout Parasitics in MOSFET Differential Pairs. This topic interests me, because back in 1982 I wrote my first IC layout automation tool at Intel that automatically created 15% of a GPU chip layout called the 82786, then joined Silicon Compilers in 1986 where IC layout automation really was push-button for users. Historically the automation of digital layout blocks came first, as analog IC layout has many more requirements than digital and was just too difficult.
For a differential pair amplifier there are a number of specific requirements to ensure robust performance, like:
Differential Pair Schematic
Matching transistor W and L values in amplifier
Interconnect parasitic balancing
Use of common centroid layout to reduce layout-dependent effects
Current mirror layout with smallest parasitic RC values
Analog IC Layout Automation
Paul showed how the Animate Preview plugin works inside of the Cadence Virtuoso environment, and that it automatically identifies schematic structures like current mirrors and differential pairs, then constrains the layout placement just like a skilled IC layout designer would do manually. You get to quickly see multiple layout scenarios within a minute or so, and each layout is already DRC clean by construction, saving you more time.
Example Analog Schematic
Clicking on the first automatically generated layout brings up the Animate Preview dialogs, showing windows for: Hierarchy, Schematic, Layout, Results and Constraints. The Layout window showed nine generated layout topographies. In the Results window there are analytics for each of the nine layouts, like aspect ratio, width, height and area. Every auto generated constraint from the Schematic is listed in the Constraints window.
Nine Layout Choices
Animate identified the differential pair from the schematic, and zooming into the schematic you can view the layout options for transistor layout like the number of layout rows used. Clicking anything in the schematic will cross-probe and highlight that device in the layout window.
Transistors M19 and M20 in the schematic define the differential pair, and the layout shows how these devices were placed in regular rows and columns known as a common centroid, which helps minimize process variations and also has matched spacings in both vertical and horizontal directions. Poly heads are defined in the same direction as part of the matching.
M19 and M20, schematic and layout
To further refine this layout and improve the vertical matching, a new dummy row was added above and below devices M19 and M20 by selecting a menu option:
Dummy rows added
The metal routing details can also be viewed in Animate, along with viewing just Poly, Metal 1, Metal 2, Metal 3, Metal 4 and Metal 5 layers so that you can confirm that interconnect in the differential pair is identical and balanced. Routing to Source and Drain nodes were visually compared, and they were balanced.
Common centroid layout was also shown for the four current mirror devices: M8, M10, M11, M12. Routing between the current mirror and differential pair is also minimized and symmetrical, by design. Examining the routing between current mirror and differential pairs revealed that the metal layers were indeed symmetrical and identical.
Current Mirror Devices
The output of the differential pair connects to two more devices, and even the placement and routing of these devices is balanced. A constraint choice was changed from Base Analog to Mirrored Base Analog to show how you can control the symmetric layout for devices on the left-hand side (Red), and right-hand (Green) side. The butterfly layout choices can be seen below:
Mirrored Base Analog
Summary
In the old days of analog IC design the circuit designer drew the schematic and maybe added some annotations or notes for the layout designer, then threw the schematic over the wall. The layout designer read the annotations, made some placements and routing, then threw the layout back over the wall to the circuit designer. Finally, the circuit designer would examine the IC layout for symmetry and matching, and request refinements, creating a loop that had to iterate until matching constraints were met.
The new method from Pulsic enables a circuit designer to quickly create a balanced and symmetric layout in minutes, not days, all because of the inherent automation designed into Animate.
Power Management ICs are a vitally important part of system design. Evidence of this is cited by a Synopsys white paper that mentions how Apple acquired a portion of PMIC developer Dialog Semiconductor that was previously their exclusive PMIC supplier. Clearly Apple had decided that PMIC design was a strategic differentiating element of their products. PMICs play an outsized role in mobile and automotive systems. PMICs are historically analog circuits, yet now contain increasing digital content. One challenge has been to see how designers combine the need for analog power circuits with CMOS digital for control.
The Synopsys white paper, titled “Calibrate and Configure Your Power Management IC with NVM IP” written by Krishna Balachandran, Product Marketing Manager Sr. Staff, talks about the history of PMICs starting with their implementation on purely analog nodes. They discuss how the advent of BCD, which combined all the device types needed for optimal PMIC design in one technology, was a game changer. The white paper offers a good analysis of the trade-offs between BJT, MOSFET and IGBT.
The white paper also focuses on the need to store critical calibration information and operation configuration settings using a secure and reliable method. It explores the many benefits that non-volatile memory IP offers for both the analog and digital elements in a PMIC design.
For the analog circuit there is variation from unit to unit that requires calibration and the storage of that information on the individual die. This ensures that the output meets specifications. Because many PMIC circuits are used in multiple applications, there is also a need to store configuration settings on the die as well.
One-time programmable (OTP) or multiple time programmable (MTP) Non-Volatile Memory NVM is ideally suited to the needs of PMICs. Antifuse NVM offers high compatibility with existing process mask layers by not requiring any new layers. It works with BCD or CMOS nodes with no additional process steps. Its high reliability, including operation at high temperatures makes it a good fit for automotive applications. NVM is also very compact which means that it further saves on costs.
Applications for NVM in PMICs
NVM is very secure from unauthorized access and tampering. Antifuse NVM bits are not readable using scanning electron microscopes or other optical or mechanical methods. This gives them a big advantage over traditional fuse technology. Fuse technology can also develop reliability issues due to bridging from electromigration. Lastly traditional fuse technology requires a lot of area, which makes it much less cost effective.
When antifuse NVM is used it is possible to emulate MTP with OTP when sufficient storage is provisioned to allow storage of multiple copies of the data. Even though not infinitely re-writable, given reasonable estimates of lifetime rewrites, OTP can work well as a practical alternative.
The Synopsys white paper also explores the tradeoffs surrounding process selection for PMICs. While a large part of the market uses 180nm BCD, increasing digital content is encouraging a move to smaller BCD nodes. Designers also face a decision of whether to migrate to a two-die solution, with one for analog and another for digital. More complex power on and power off requirements, such as power ramping and standby modes is causing digital content to grow.
The Synopsys white paper is thorough and does a good job of articulating the issues surrounding PMIC design. PMICs are definitely a key competitive component in most systems today. Designers need to look at every opportunity to add needed features and optimize them as they reduce costs and ensure high reliability. OTP NVM technology is proving itself as a key element in this effort. The full Synopsys white paper is available here for download.
Semicap is in some ways the unsung hero of American global dominance in semiconductors. The US punches above its weight in terms of market share compared to demand, but specifically in three categories. EDA, IP, and Equipment.
I hope to write about everything there can be said about semiconductors, and EDA is a place I understand a bit but not as much as I’d like. I still really like the Scuttleblurb EDA primer – and refer back to it from time to time. But Semicap – that is a place I feel pretty confident about, and I think the industry structure, capital returns, and defensiveness of the businesses is truly attractive. It’s a great subsector and always seems to reasonably priced.
Industry Overview and Map
First – I am going to start with this industry map and kind of break it down further. I really like this simplistic semiconductor industry map @Fritz844 made on Twitter (he seems to have deleted it).
You can see here where the Semicap companies exist – and who their key customers are. There is another level deeper I wanted to make a graphic for. Also “mid-end” semicap is something that is kind of emerging and new, so if you haven’t really heard of it before that is okay. I would put advanced packaging firmly in this segment, and this is where the back end is starting to look a lot more like the front end. More on that later.
I think this is a decent industry map, with the customers on one end (purchasers) and the suppliers on the other (Semicap and materials). I think right now there is a bit more blurring of Semicap lines than there was in the past, with materials and mid-end kind of being the emerging points of relevance on the map. Obviously, the front end is going to continue to be the most important part, but with the end of Moore’s law, we increasingly need new materials, new technologies (advanced packaging!), and new methods to keep the pace of improvement constant. If you have no idea what Front End, Back End, or Mid End mean, that’s where the next part comes into play.
The 10,000+ foot view of Semicap
My favorite quick infographic on how a semiconductor is made is from the ASML Annual report. I will briefly walk through a few of the steps.
Let’s start with Photoresist. The photoresist is a light-sensitive polymer put on top of a silicon wafer, and when exposed to light it turns into a soluble material. The exposure to light step is called lithography, and using light, they can print materials onto the wafer. This process is similar to old fashioned photography and film, and the light is shone through a lens called a photomask and imprints it’s image onto the film or silicon wafer.
After exposure, you smooth out the resist using a bake, which helps development. Development is similar to developing a photo and uses aqueous bases to create the shape of the photoresist profile. Next comes either etching, deposition, or ion implantation. Each has a different role in building a semiconductor transistor pattern, such as subtracting, adding, or doping the substrate.
Etching is the most common, and etching is usually performed using wet chemicals or plasma and is commonly used to dig deeper trenches. The photoresist material resists the etching and protects the covered material, and then they can print the process onto the substrate.
Last is stripping the photoresist, to then move onto another cycle or step in the fabrication process. Each of these steps is often to just print a single layer. And many modern semiconductors can have hundreds of layers built on top of each other, and of course, any single mistake will create a defect in the semiconductor. This explains why they are obsessed with cleanliness in the fabs. A single micron of dust will destroy a die and ruin yields.
For me – I think of building a semiconductor like laying a city filled with skyscrapers one floor at a time. Each step in the process either adds or subtracts a floor. After hundreds of steps, you then take a step back and you have your fully built “city”, complete with the hundreds of miniature skyscraper-like transistors.
Everything I just described here is what is called the front end of semicap. The front end usually refers to the equipment that goes into the physical transistor creation from silicon and tends to be the largest source of spending for fabs. The emerging “mid-end” is post transistor, but pre-die-cutting or advanced packaging.
With wafer-level advanced packaging such as CoWoS processes and more, parts of packaging that were firmly in the back end historically are moving towards the front end. This is really important and likely one of the best opportunities in growth and misunderstood businesses for now.
Lastly the backend. After the semiconductor leaves the fab, the product is not done yet. There are more steps of assembly and testing that have to go into making a working end product from pieces of silicon. Even the typical CPU core you see has some level of packaging applied to it after fabrication. This has historically tended to be more cyclical and considered a worse business at the end of the tailwhip of the semiconductor supply chain. But with the importance of packaging rising in Heterogeneous compute, many back-end companies have been thrown a strategic lifeline.
Each of these steps is “owned” by a particular company. We will be diving into market share, positioning, and company descriptions in focused paid write-ups – but for now, know that the top 5 semicap companies have approximately ~65% market share. This is an oligopoly and a profitable one at that. There are some niches in each business that are truly wonderful. I think you’ll also learn a lot about the core science, the barriers to entry, and some of the most wonderful technology we’ve come up with to date. These will all be paid posts to come.
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The term Metaverse has been a hot topic of conversation recently, with many tech giants like Facebook and Microsoft staking claims. But what is The Metaverse?
Author Neal Stephenson is credited with coining the term “metaverse” in his 1992 science fiction novel “Snow Crash”. He envisioned lifelike avatars who live in realistic 3D buildings and other virtual reality environments. Correspondingly, in a technical sense, Metaverse is another name for the Internet of Everything (#IoE), a concept started in the early 2000s, leading to the Internet of Things (#IoT) and its applications a scaled-down version of the IoE. Since then, various developments have made milestones on the way toward a real Metaverse, an online virtual world that incorporates augmented reality (AR), virtual reality (VR), 3D holographic avatars, video, and other means of communication. As the Metaverse expands, it will offer a hyper-real alternative world or what Comic fans call the parallel universe. But this description is like talking about “Frontend “in apps development only without explaining the “Backend” side of the apps. To understand that side of this new X-verse, we need to look at Metaverse from a different perspective.
Different Perspective of The Metaverse
The Metaverse “is bringing together people, processes, data, and things (real and virtual) to make networked connections more relevant and valuable than ever before-turning information into actions that create new capabilities, richer experiences, and unprecedented economic opportunity for businesses, individuals, and countries”. In simple terms, the Metaverse is the intelligent connection of people, processes, data, and things. It describes a world where billions of objects have sensors to detect, measure, and assess their status, all connected over public or private networks using standard and proprietary protocols. The main pillars of The #Metaverse, as depicted in Fig. 1, are:
People: connecting people in more relevant, valuable ways;
Data: converting data into intelligence to make better decisions;
Processes: delivering the right information to the right person (or machine) at the right time;
Things: physical and virtual devices and objects connected to the Internet and each other for intelligent decision-making.
Figure 1: The pillars of The Metaverse.
Challenges Facing The Metaverse
No new technologies or concepts come without challenges, and the Metaverse is no exception:
Identity Management: it is difficult to confirm ID in current Web 2.0 apps; with Metaverse, the problem scales up as we expand the use of the products and services; the last thing you want is to create a wild west in Metaverse.
Security, Safety, and Privacy (SSP): As devices/people get more connected and collect more data, accelerating the Metaverse expansion at a speed close to the speed of the real universe, privacy, safety, and security concerns will increase too. How companies decide to balance customer SSP with this wealth of Metaverse data will be critical for the future of the Metaverse and, more importantly, customers’ trust in the Metaverse and any future X-verse versions.
Finance in Metaverse: using cryptocurrency is a challenge by itself; using it as a way of payment in Metaverse will add more complications to what is still an unregulated payment system, one of the options to overcome this is to consider #CBDC (Central Bank Digital Currency)
Laws, regulations, and protections: new world and new territory for the law to explore and define the responsible parties and create new regulations to protect everyone using Metaverse, including Intellectual Properties with the newfound businesses like #NFTs
The emotional and mental impact of living in Metaverse: the same issues of non-stop social media usage and online gaming will transfer to the Metaverse on a large scale with another dimension added with near real-time interactions, this could create a lot of mental issues in the real world, and the line between real and imaginary world will be blurred with actions and words used in both worlds.
Standardization of the Metaverse: this is usually one of the toughest parts in the early lifecycle of any new technology as everyone wants to be the “standard” and dominate the market; standards will cover all hardware/software, processes, protocols and make interoperability fundamental to the design and implementation of the Metaverse.
The Future?
Data are embedded in everything we do; every business needs its flavor of data strategy, which requires comprehensive data leadership. The Metaverse will create tens of millions of new objects and sensors, all generating real-time data which will add more value to their products and services for all the companies who will use Metaverse as another avenue of business. As a result, enterprises will make extensive use of Metaverse technology. As a result, there will be a wide range of products sold into various markets, vertical and horizontal, an endless list of products and services.
For example, in E-commerce, the Metaverse provides a whole new revenue stream for digital goods in a synchronous way instead of the current traditional 2D way of clicking and buying. In human resources (HR), significant training resources will be done with virtual reality (#VR) and augmented reality (#AR) that are overlaying instructions in a real-world environment and giving somebody a step-by-step playbook on how to put a complex machine together or run a device or try a new product all will be done with virtual objects at the heart of the Metaverse. While in sales/marketing, connecting with customers virtually and sharing the virtual experience of the product or service will be common similar to our virtual meetings during the past two years in the middle of Covid, but the Metaverse will make it more real and more productive. Crypto products, including NFTs, will be the natives of the Metaverse, adding another block to the Web 3.0 puzzle.
The pandemic forced us to be more online and accept many actions to be virtual, which was like a preview for the Metaverse in 2D; the real Metaverse is 3D with time as the 4th dimension. Still, in the Metaverse, we control time and space because we crate both in the Metaverse.
Finally, similarly to Cloud Computing, we will have Private-Metaverse, Hybrid-Metaverse, and Public-Metaverse with all possible applications and services in each type. Companies will benefit from all options based on their capabilities and needs. The main goal here is to reach Metaverse as a Service (MaaS) and see a label of “Metaverse Certified “on products and services.
Dan is joined by CEO of Cormani Wally Rhines. Wally discusses the recent strategic investment in Conrami made by Applied Ventures (the venture capital arm of Applied Materials Inc.). Wally explores what type of business models and manufacturing optimization can be made possible if fully homomorphic encryption (HFE) can be enabled with Cornami technology.
The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.
I had a follow-on discussion with Alex Yoon from our podcast last year. He is as a Head of Strategic and Emerging Technologies and partnerships at Intermolecular, part of EMD electronics.
Prior to joining EMD electronics, he was Senior Technical Director at Lam Research, led activities in emerging memory and novel materials in New Product Development, Corporate Technology Development and Advanced Technology Development groups. Prior to Lam, he was technology manager for WCVD/WALD at Applied Materials. He holds BS in Chemistry/Materials Science from UCLA and PhD in Chemistry from UC Berkeley.
In our podcast we discussed semiconductor materials innovations. This time we are talking about integrating materials solutions.
What is the rationale for integrating materials solutions? Why now?
The Semiconductor industry is facing many challenges and opportunities – all of which demand faster product innovation. Integrating the right materials solutions helps enable differentiation.
Point solutions may not solve present day device, integration and process technology needs / in an efficient, rapid and complete manner. Integrated materials solutions aim to solve complex integration challenges by collaboration and co-optimization of individual solutions to give better, faster solutions.
Severe reduction in design, device and process margins for present day semiconductors creates the need now.
How did customers solve these problems before integrated materials solutions was available? Why is that approach not completely viable?
Previously these problems were solved sequentially, especially when materials suppliers were involved. For example, first develop the precursors, the deposition technique and the resulting thin film. Then develop the slurry, pad and CMP process. This sequential process is inefficient and could potentially lead to unnecessary/inadequate optimization especially when integration considerations are missed during optimization of just one material.
What are the top 3 benefits to adopting integrated materials solutions approach?
Better convergence to integration driven needs, better and faster materials solutions, tackling integration issues early on in the process, and deployable solutions developed with process integration in mind help achieve higher order key performance indicators. All of which leads to faster product development and innovation for customers.
How does the previous and proposed integrated solutions approach compare? Benefits vs risks?
Traditionally, the approach was siloed between the different processing steps. This allows to have deep technical experts push the technology further, however the downside is that the solutions only come together in the integration team. With Integrated solutions, we leverage the position of EMD Electronics with all the various in-house materials, using our understanding of the materials and the ability to quickly iterate, so that we keep the deep technical experts involved while breaking up the silos between the different disciplines.
Benefits of this approach is we can offer better, faster solutions and better convergence to integrations needs of customers. On the other end, the risk is that this model changes engagement model between chip makers/foundries and materials suppliers. Requires transparent and trust-based interactions to understand capabilities and customer may be somewhat reluctant to share their insights.
What is an example where you can co-optimize multiple steps towards an integrated solution?
We have multiple examples of co-optimizing multiple steps. Such as deposition of thin film and planarization, deposition of materials and etch gases, co-optimization of atomic layer deposition (ALD) and atomic layer etch processes (ALE)
How do customers engage with you specifically to take advantage of this integrated approach? How long is the engagement?
Customers highlight a process technology needs to include a discussion on integration challenges and specifications for individual process steps. EMD Electronics will then assess and respond with specific options, actions and timelines. Once we mutually align on the Statement Of Work, or Joint Development Agreement, we can collaborate via frequent and regular communication meetings to realize the integrated materials solution. The engagement depends on the scope and deliverables but can be typically 6 months for simpler project and longer for more complex or involves new materials development.
What is the future for integrated materials solutions? Do you expect to go beyond the process module level?
Integrated materials solutions are not limited to any specific or limited number of levels of abstractions. Currently we are focusing on integrated materials solutions based on device and process integration needs and see that our customers find value in this. We will listen carefully to feedback from our customers and use our core strengths in materials innovation to best serve them.
Intel recently released an exceptional video providing an insightful chronology of MOS transistor technology. Evolution of Transistor Innovation is a five-minute audiovisual adventure, spanning 50 years of Moore’s Law. Some of the highlights are summarized below, with a few screen shot captures – the full video is definitely worth viewing.
The speaker is 16+ year Intel veteran Marisa Ahmed, a Member of the Technology Leadership Marketing Team. Marissa is responsible for building technology marketing strategies and activities in support of Intel’s process, packaging and manufacturing capabilities.
1971
The figure above establishes a baseline for the MOS field effect transistor, circa 1971.
(Note the additional supplemental info provided with the transistor cross-sections that follow – e.g., the total number of transistors released; the number of metal layers for the process generation; the exposing wavelength for lithographic patterning; the wafer size; and, the related Intel product families.)
Polycide and Salicide: 1979-81
With ongoing Dennard scaling of the device gate length, the sheet resistivity of the polysilicon gate material was increasing. Similarly, the transistor drain/source series resistance (Rs, Rd) was increasing. The contact resistance (Rc) to the metal layer was also increasing, due to the scaling of the S/D junction depth. To address these problematic parasitics, a process innovation emerged to create a silicide. A refractory metal such as Titanium was deposited and alloyed at elevated temperature with the exposed silicon. (Salicide is a composite term for “self-aligned silicide” – the deposited metal does not react with the adjacent dielectric materials.)
STI: 1995
The device electrical isolation and surface topography underwent a significant change, in the transition from local oxidation of silicon (LoCoS) to shallow trench isolation (STI).
LoCoS was a process method where the field oxide isolation between devices was formed by patterning a hard mask over the device area, and exposing the field to an oxidation environment. Oxygen would diffuse from the high-temperature environment through the growing field oxide layer to reach with the silicon crystal at the oxide-substrate interface. The resulting oxide profile was a tapered (“bird’s beak”) surface topography, better for metal traversal between devices.
To facilitate further scaling, a new process for field oxide separation was introduced. STI leveraged major improvements in anisotropic dry etching technology (with near vertical sidewalls) combined with chemical vapor deposition of dielectric materials.
Aluminum à Copper
A watershed (non-device) process enhancement in the late 1990s was the transition from Aluminum metallization to Copper. Dennard scaling continued to enable greater device current and lower device capacitances. This era was marked by the transition from gate fanout load-dominated circuit delay to significant contributions from the R*C interconnect delay from the driving gate output to the fanouts. The need for interconnects with improved resistivity and electromigration robustness necessitated the transition from Al to Cu.
Concurrent with that material transition, a major shift in interconnect patterning was required. Aluminum as the primary interconnect involved a rather straightforward deposition, lithography, and subtractive removal process flow. Due to the difficult chemistry associated with dry etching of copper – e.g., corrosive gases, few volatile copper-based reaction products to pump out – a damascene patterning method was required. The dielectric to surround the metal was deposited, a trench was etched in the dielectric (and interlevel dielectric below for the vias), then copper was deposited in the trench through electroplating.
In addition to the additive damascene process replacing the subtractive Al etch method, it was also therefore necessary to evolve the chemical-mechanical polishing (CMP) process step. The wafer surface with the deposited Cu is placed face down onto a polishing pad, which rotates at a low speed. A rotating piston at higher RPM provide an appropriate downward force on the wafer (Newtons/cm**2), and a slurry is introduced onto the pad. The slurry consists of both a chemical solution and a fine grit. The chemical is intended to selectively react with the material to be removed – Cu, in this case – while the mechanical polish removes the result of the reaction. An extremely flat surface topography is produced. As shown in the figure above, as well as the succeeding figures, CMP has enabled a much-needed increase in the number of metal layers available for interconnecting the scaled circuit density.
Gate and gate oxide enhancements
Device evolution encountered issues with continued scaling of the gate oxide thickness. The influence of the input gate electric field on the device channel requires scaling the gate oxide capacitance: Cg ~ ((K*E0)/t), where K is the relative dielectric constant and t is the gate oxide thickness. As the gate oxide became thinner, gate tunneling current through the device input increased. To equivalently increase Cg without the issues of reducing the thickness, alternative high-K dielectric materials replaced SiO2 for the gate oxide.
Scaling the traditional polycrystalline silicon gate material was resulting in higher resistivity and greater sensitivity to non-uniformity in the polySi grain size, distribution, and impurity concentration. A replacement metal gate process step was introduced, displacing polySi as the gate material. (For more info on this rather difficult step, do a follow-on search for high-K, metal gate “HKMG gate-first versus gate-last” process; the term replacement in the figure above refers to a gate-last flow.)
FinFET: 2011
Intel amazed the industry with its aggressive adoption of a new transistor topology at the 22nm process node – the FinFET (also known as the “tri-gate FET”).
The traditional planar S/D channel topology had an increasing issue with (sub-channel) leakage current between source and drain when the device was “off”. To reduce the sub-threshold leakage, a device topology was required where the gate input provided greater electrostatic control over the channel. The vertical channel “fin” has the input gate traversing over the sidewalls and top. In the figure above, a single gate inputs traverses over three silicon fins to be connected in parallel – the channel current flows through the vertical fins. The thickness of the fin is sufficiently small such that the gate input electric field control reduces the sub-threshold leakage substantially, which has enabled much greater battery life for laptop and mobile electronics.
Gate-All Around (GAA) Ribbon FET: Intel 20A in 2024
To further improve the electrostatic gate control over the channel, another major evolution in the transistor topology is emerging to replace the FinFET. A gate-all-around configuration involves a vertical stack of electrically isolated silicon channels. The gate dielectric and gate input utilize an atomic layer deposition (ALD) process flow to surround all channel surfaces in the stack.
Intel will be releasing their GAA Ribbon FET 20A process in 1H 2024.
Summary
The evolution of the field effect transistor over the past 50 years is rather amazing. The figure below illustrates this progress, with the devices drawn to scale.
This evolution was enabled by the innovative ideas and hard work of research and development teams throughout the industry, with expertise ranging from materials science to chemistry to optical lithography to the physical of deposition/etch process steps. Rather incredibly, this progress shows no signs of stopping anytime soon, absolutely.
There’s a lot to be said for staying power. I’ve met many people in my career who simply resonate with a company – their products, culture, and direction. People like this build an organic knowledge of the company’s products and its customers. They contribute to a culture that helps enable great companies. Keith Guetig is one such person at Samtec. He joined the company 26 years ago as an engineer, and today he directs the new product roadmap. I had the opportunity to interview Keith recently about his journey at Samtec. Read on to learn what a passion for innovation can accomplish.
What drew you to Samtec?
Samtec has a service-driven culture combined with a passion for innovation and new technology. These are desirable attributes for a young engineer looking to kick off a career.
How long have you been there, and how has the journey been so far?
I began working at Samtec as an engineering co-op in my fall semester of 1995. Therefore, I’m homegrown. I’ve now been with Samtec for 26 years. My career has included three phases. I began in manufacturing engineering. This portion of my career included automation design, which I found fascinating. My second phase was technical application engineering for our newest, most advanced products. Both hands-on and directing a growing team. And today it’s Product Management leadership. Our future growth is dependent on correctly setting the new product directional compass today.
With regard to high-performance cables, what are the trends between traditional and optical technologies?
The trend isn’t pointing toward a “winner” between Copper and Optics High Performance Cables. The trend is more of both. And the applications and industries that drive the demand – AI/ML, Data Center, ASIC evaluation and development, Automotive and Transportation, Embedded Computing, etc. – are growing and diversifying, which is a good thing.
Do certain applications drive one type of technology vs. the other?
The easy answer here is the required reach of the channel (advantage fiber for long reach). But others include size and flexibility within a bundle (advantage: optical fiber), thermals (advantage: copper), and cost (advantage: copper, usually).
Over the past decade, we’ve seen explosive growth in design complexity at the chip level. Have you seen similar trends for high performance channels?
Certainly yes. A second order effect of this is the challenge of signal loss routing away from the chip package. This challenge creates an inflection point in our market: The utilization of inside the rack high-speed ultra-low skew twinax copper cable assemblies like Samtec Flyover systems, passing traffic that previously was handled in the PCB. This enables a full rethink of legacy architectures; this is the story.
What types of requirements have seen the most demand for improvement?
As signal integrity challenges increase for chip package substrate and PCB, it translates to less allowable performance margins for connectors and cable. There’s also a growing demand for one hundred percent signal integrity characterization for finished products, right on the line, not in the lab. This is a big challenge in the connectivity industry, albeit we already have this capability at Samtec thanks to forward planning many years ago.
Simulation models for channel components seem quite important. What is Samtec’s view of this?
We utilize Ansys HFSS for all our new product development; the correlation with measured signal integrity performance is highly impressive. The bottom line is this: We can iterate a connector/cable design 100+ times before we ever tool anything up. Therefore, we precisely tune the design to exactly meet the target performance attributes. Our customers love this.
Looking out five years, what will be the most impactful new design requirements that Samtec will address?
It’s a bundle of applications, requirements and solutions that overlap. Some of these include:
Connectivity interfacing directly to the chip package
Advancements in low loss and phase stability cable plus material advancements that further mitigate crosstalk, all enabling 224G and beyond
