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Webinar alert – another break in the memory wall

Webinar alert – another break in the memory wall
by Don Dingee on 06-13-2016 at 4:00 pm

A couple months ago we heard from another vendor in a webinar on HBM and breaking through the “memory wall”. Next week Open Silicon weighs in on the topic in a webinar with partners SK Hynix and Synopsys.

Those who caught the NVIDIA keynote at 53DAC, or any of their other recent presentations, see how big a role HBM is playing in GPU technology. Per some of the comments in my last blog on this topic, I think there is some confusion over exactly where else HBM fits. The advantage of HBM is achieved in a very short and very high bandwidth bus interface, most often packaged within a single part in a multi-die format.

HBM is the natural evolution of PoP DRAM packaging often seen in mobile SoCs, with even tighter integration and shorter trace lengths, lowered capacitance, and less power consumption. It’s not intended as a direct replacement for large-scale external DRAM often in DIMM form factors; by the time traces run that far including through two sets of pins, the performance advantages are mostly undone.

Two things are interesting about this event. First is the emergence of an alternative group of partners aligned around SK Hynix. However, I believe their technical story is exactly the same, and can in fact be traced to a single document that most HBM proponents are working from.

I’m talking about the “Multi-Die IC User Guide” authored by Herb Reiter, who is moderating this event. Herb is quite passionate about the system scaling opportunity through multi-die integration. The fact that Herb and by association EDAC is out in front of this event is the other significant development here. (The prior HBM webinar we covered may have just had way too many speakers, there were five companies represented during that hour.)

One tidbit in Herb’s document is the use of redistributed chip package (RCP) for the NXP MR2001, a 77 GHz radar transceiver chipset for automotive. In other words, this particular discussion may center on HBM, but the real insight may be in use of multi-chip packaging techniques. I’m excited to see what these folks have to say.

To register for the event, visit: HBM – Breaking Through “The Memory Wall”

About Open-Silicon
Open-Silicon transforms idea into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software, and IP — and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing, and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed over 300 designs and shipped over 120 million ASICs to date. Privately-held, Open-Silicon employs over 250 people in Silicon Valley and around the world. www.open-silicon.com

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