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Top Ten #53DAC Highlights

Top Ten #53DAC Highlights
by Tom Dillinger on 06-13-2016 at 12:00 pm

Here is a very subjective list of the Top 10 logistical and technical highlights from DAC’53.

(10) With DAC attendance down from its peak days, the Austin Convention Center served as an excellent venue. There was good participation from companies with design centers in the “Silicon Hills”. And, I saw colleagues from Silicon Valley, SoCal, and overseas who made the trip, as well. Kudos to the DAC Committee and sponsoring companies for the free parking!

(9) SWAG is actually an acronym, short for Souvenirs, Wearables, And Gifts.

I’ve never really understood why exhibitors give away pens, stuffed animals, stress-relief squeeze balls, even drumsticks. Then again, since I’m mentioning it, I guess this form of advertising works.

(8) The $99 Design + IP Track registration fee is a great deal.

Although 15 minutes is perhaps a bit too short for many Design Track presentations, there is an opportunity to follow up with the presenter at the evening poster session. Now that the conference Proceedings are distributed electronically, it would be nice if the Design Track and IP Track slides were available for review prior to the conference, rather than posted afterwards.

(7) The committee needs to establish better guidelines and standards for presentation charts – there are still simply too many slides that are illegible from the back of the room.

(6) The keynote from Professor Ken Shepard at Columbia Univ. was fascinating. The potential to harvest (and store) electrical energy by controlling biological cell membrane ion transport to power electronics could open up new opportunities, despite the very low duty cycle of actual computation to energy charging.

(5) As you might imagine, the growth of electronics in automotive applications was a prevalent theme of the conference. And, not all the focus was on autonomous driving. Monday’s keynote from Lars Reger at NXP provided several illustrations of advanced inter-vehicle and infrastructure communications that would also provide significant benefit.


Take the NXP “RoadLINK” feature. For example, you’re likely aware that race cars draft behind a leader to save fuel – consider the fuel-saving benefits of a set of freight trucks linking into a “platoon” (or “convoy”, for you old-time CB’ers). A rather aggressive distance is maintained between the trucks, enabled by syncing up to the forward vision and braking controls of the lead truck.

And, if the infrastructure were in place, stoplight timing in a city would be adjusted to green light the oncoming platoon. (Here’s a link for more info.)

I concluded there are lots of technology options in the automotive area with significant ROI, but am also anxious about the tremendous coordination required in this country among political and industry organizations to address the corresponding costs and schedule. (Europe seems to be well ahead of the U.S. in this regard.)

Coincidentally, this month’s issue of IEEE Spectrum has an enlightening article about the emerging concerns about vehicle manufacturer and driver liability in a world with increasing automotive automation (especially, relative to the vehicle software). I was optimistic that my car insurance rates would go down in the future – now, I’m not so sure. 🙂

(4) IP security was also a major topic of discussion. Clearly, the IP providers are concerned about the potential loss of revenue due to IP theft, and the loss of traceability for edits to (configurable) IP variants.

One paper I attended presented a proposal for collaboration between IP providers and tool developers, to support the use of encrypted IP models. The presenter reminded the audience that encryption will be needed across the gamut of models. He highlighted that encryption would not only apply to functional verification and synthesis, but also the full DFT tool suite. (I’m still trying to get my head around an encrypted fault diagnosis tool.)

(3) On the EDA vendor exhibit floor, electrical analysis of SoC’s was the hot topic.

It should be no surprise to regular Semiwiki readers that I*R power distribution voltage drop and power/signal ElectroMigration (EM) are critical sign-off steps in current fab processes.

Specifically, to prevent long iterative loops between implementation and electrical analysis, the physical design platform needs to integrate “in-design” analysis engines, ideally with corrective recommendations provided to physical designers.

(2) To address the burgeoning IoT application market, it should also be no surprise that power management and power optimization techniques were front-and-center. Several designs had adopted increasingly complex clock grid/tree distribution methods, with multi-level gating circuit topologies.

Of note was that these clock networks had to be successfully managed across multiple hierarchical levels of the physical floorplan, and (ideally) with commonality across multiple instances of the same core IP.

The handling of global signal/clock buffering and routing passing through and around block designs remains an intricate data management problem.

(1) And, to me, perhaps the most exciting announcement at DAC could be found at Samsung’s exhibit, where they were demo’ing an SoC with an integrated magnetoresistive (MRAM) memory array. This very unique and attractive technology option will be available from Samsung Foundry in 2018 – look for another Semiwiki article on this announcement shortly.

DAC has certainly evolved throughout the years. It remains the most important event for our industry, to learn of the newest developments – whether that be new foundry technologies, new EDA vendor tool features, or unique and interesting design approaches. The glimpse into active research and its potential future applications is pretty cool, too.

See you at DAC’54 in Austin next June.

-chipguy


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