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Imec’s Process Secret Decoder Ring

Imec’s Process Secret Decoder Ring
by Paul McLellan on 07-12-2014 at 11:00 am

To wrap up Semicon West, let’s go back to Monday and the imec presentations. In fact, An Steegen’s presentation titled The Semiconductor Roadmap. She covered a lot of ground, but some of her slides contain a wealth of information. Let’s look at the options for 10nm, 7nm and a little 5nm, what imec call N10, N7 and N5 (which makes sense since there isn’t anything 10nm on a 10nm process, it just represents a name that scales down from larger nodes where the dimension of the process really did correspond to the size of the transistors).

This graph above (click to enlarge) is a little complex but worth understanding. What it shows is the various tradeoffs we can make at each process (the green lines) on metal2 pitch and contacted poly pitch. The horizontal and vertical lines show the limits of lithography: 193i LE3 (aka litho-etch-litho-etch-litho-etch, so triple patterning), SADP (self aligned dual patterning, also sometimes called sidewall image transfer), single exposure EUV (so single patterning), 193i SAQP (self aligned quadruple patterning) and high numerical aperture EUV single exposure. We would like to keep the metal pitch above as many of the the horizontal lines and the CPP pitch to the right of as many vertical lines as possible.

 If you extend that approach to a lot more layers then you end up with the table above (which assumes no EUV). Note that on metal1 it is assumed at N10 you can have two-dimensional metal (metal can run horizontally and vertically) but that at N7 it is assumed to be one-dimensional (either horizontal which is a bit simpler but has an area impact since 7.5 track standard cells are not possible, or vertical which is more complex but has better area since 7.5 track standard cells are feasible, and some other stuff; click on the picture on the right for more details). There is a lot of information in this table. For example, at N10 the fins require self-aligned double patterning with a single patterned cut mask. At N7 it gets more expensive: self-aligned quadruple patterning with an LELE (double patterned) cut mask. You can see the mask counts at the bottom (just for the first few layers, more depending on how many layers of metal get put on top of that).

This table assumes EUV happens at N7 and is used in a hybrid process along with 193i immersion lithography too. EUV is used to avoid almost all the block and cut masks and so reduces the number of masks significantly.

One advantage imec has over most of us is that they are knowledgeable about many of the decisions made by the various manufacturers at each process generation. There is not only one answer. For example, at 16nm some people have apparently opted for 64nm metal pitch and others for 58nm, which you can also read off the table (the white box at the top of the dark blue bar). The above graph shows those choices. Actually only the white boxes on the tops of the bars are really relevant, they show the range of values that are possible at that node for the 3 parameters, the FinFET spacing, contacted poly spacing and metal pitch.

As I said, there is a huge amount of very detailed information contained in these graphs and tables, it is the magic decoder ring for the semiconductor process roadmap.

Also read: IMEC Technology Symposium

More articles by Paul McLellan…

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