Sales says this next IoT project is going to be huge. Engineering isn’t so sure. Marketing says we should pilot it to find out. If it were just software, it might not be such a problem, but with hardware comes investment tradeoffs. Without guaranteed volumes of millions of units, are ASICs a realistic option to hit aggressive size, power, and cost targets?
Those who follow me have seen my position: we need a new class of chips specifically designed for IoT requirements. However, I feel your pain – I was a director of marketing reporting to a VP of engineering once upon a time, and we learned to spend engineering resources very wisely. Incremental innovation is a lot easier; one has actual volume, pricing, and cost data to go on. Breakaway innovation is tougher, with a lot of additional variables from having the right requirements to finding multiple customers to beating competitive initiatives.
In a recent webinar, EDA veteran Dan Ganousis – who most recently has been creating geosurvey drones at Iron Ridge Engineering – has returned to help find breakaway answers for IoT projects. In his opening comments as moderator for this event, Dan introduced the topic of IoT design using customized ASICs very effectively. One of his key points was that in mobile, it was custom SoC design that made the software stand out competitively, something readers of my book “Mobile Unleashed” know well from the exploits of Apple, Qualcomm, Samsung, and others.
Ganousis tells the story of seeing a skier on the slopes with a Raspberry Pi in a box strapped to each boot, with 3 sensors per boot. Maker modules are wonderful – for some things. Making the leap from an IoT prototype to a cleanly executed product takes some intestinal fortitude, but perhaps not as much investment as we’ve been conditioned to believe. By leveraging mature processes, open source tools, multi-project wafer services, and a more cost effective processor core, designs of around 50K units become feasible.
Cortus believes they have part of that solution in a family of 32-bit RISC cores, and according to VP Roddy Urquhart they have shipped 800M of them so far. One of their more recognizable design wins is the Atmel WINC1500B, a Wi-Fi/Bluetooth combo part that has found its way into the Adafruit Feather designs with their Arduino libraries. They also list HiSilicon, Intel, LG, Rockchip, Spreadtrum, and others on their customer roster.
Urquhart is applying a fascinating argument; one I’ll call security through un-popularity. (That’s meant as a compliment, along the lines of Erika Napolitano’s book “The Power of Un-popular”, a call for more focus and differentiation from the crowd. Harsh language, but a great read for marketers.) He says that software-based security can end up less secure – it’s often in shared memory, on top of an insecure OS, and is fluidly modifiable. He claims a deeply customized solution can be far more secure, albeit one less modifiable. It’s the difference between an Android application processor that masses of developers target (often ARM Cortex-A) and a baseband processor that only carriers and a select few others deal with (perhaps ARM Cortex-R, CEVA-X, or a Qualcomm core).
It’s not a completely new idea, and Cortus is not a startup per se with a 10-year history. There are parallels to Synopsys ARC and Cadence Tensilica and other cores. However, Cortus is now after a new audience: an IoT boutique with a great software idea and little to no experience developing ASICs.
The webinar is geared to help these folks relatively new to ASICs understand their options for mid-volume designs, a logical progression to the post-maker stage where optimization of size, power, and cost has high value. Cortus is also offering the benefits of teaming with a smaller, highly focused company – one stop for tools, support, and resources. For example, during the webinar Tim Davis of Aspen Logic describes an FPGA-based development board with a Xilinx Spartan 6 accommodating Arduino Due shields (looking for ARM makers to cross over). The advanced Cortus APS25 core takes only 29% of the FPGA, leaving plenty of room for other IP.
In other pluses, this webinar is in the clear (no registration required), and there is a Monty Python reference in one of the slides (something about catapulting cows past security):
If you’re struggling with the idea of ROI for a customized ASIC on a post-maker IoT project, this is worth a watch for a systems-level discussion.Share this post via: