All-Embracing Multiphysics Analysis for Chiplet-Based SystemsWhat systems can accomplish by combining semiconductors, AI,…Read More
How Samtec Blazes a Trail to 224/448 Gbps at DesignCon 26I recently covered what Samtec was doing at…Read More
Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume FabsA deposition chamber drops out of production at…Read More
AION Silicon: Architecting Smarter SoCs with RISC-V: Balancing Performance, Flexibility, and Risk Architecting Smarter SoCs with…Read More
AI-native Virtual Chiplet Eco-systems: Shift Left, Shift Up, and Shift Out to accelerate Chiplet adoptionSystems-in-package (SIPs) with 2.5D and 3D heterogenous integration,…Read More
If you pass by Grenoble tomorrow (Tuesday 4th Dec.) and go to IP-SoC 2012, then you should attend this panel at 4pm in the Auditorium (you can’t miss it, it’s the larger room at the registration level).
If you are Designer, Architect, Project Manager, Marketing… working for a chip maker, please prepare questions!… Read More
It seems that Ateris vs. Sonics war, initiated by Sonics in 2010 on the legal battle field, is now continuing on the marketing field, as far as I am concerned, I prefer the latter, as I am an engineer and not a lawyer, and I must say that playing in the marketing allow both companies to extract the most attractive features of their products.… Read More
ST Microelectronics announced yesterday that it would have a conference call on December 10th to announce its strategy going forward. ST has been struggling the last couple of years, with revenues down year to year. From 2010-2012 (the last an estimate of course) it did $10.3B, $9.6B and $8.4B so it has shrunk nearly 20% in 3 years.… Read More
IC designers using advanced nodes are acutely aware of how variation effects in the silicon itself are causing increased analysis and design efforts in order to yield chips at acceptable levels. Four authors from Solidoare so passionate about this topic that they combined their years of experience into a book that I had a chance… Read More
The Accellera Systems Initiative, most well-known for driving the standardization of various aspects of Verilog and SystemVerilog before handing the standards off to the IEEE, has announced that nominations are open for the 2013 Technical Excellence Award. This recognizes outstanding contributions in the creation of EDA… Read More
LTE (Long Term Evolution) is the true 4G standard for cellular and, over time, wireless internet. In fact it is several different standards with different levels of performance. LTE will eventually be the only technology used in cellular, voice will simply be Voice-over-IP (VoIP, the same technology that companies like Skype… Read More
Calypto has an interesting webinar coming up about Minimizing RTL Power Through Sequential Analysis. It is next Tuesday December 4th at 11am.
Insert standard paragraph about how power is the new timing, everyone worries about power, battery life in smartphones, half-empty datacenters.
You probably already know about clock… Read More
This is a follow up post to 8 Reasons Why I Hate my iPhone 5. The reader’s digest summary is that I started my smartphone journey with Android and became accustomed to the Android way of doing things. It was a difficult jump into the Apple ecosystem. I’d wager that the vast majority of smartphone users stay with their initial platform,… Read More
Since the beginning of the semiconductor industry, improving the rate of yield learning has been a critical factor in the success silicon manufacturing. Each fab has dedicated yield teams that look at the yield of wafers manufactured the previous day and attempt to find the root cause of any unexpected “excursions.” In earlier… Read More
I met Frank Wiedmann on LinkedIn because we are both members of the Analog Mixed Signal group, and he has an interesting background in AMS IC design.
Since he lives in Munich we conducted our interview by email.… Read More
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Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?