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TSMC 2026 OIP Ecosystem Forum Summary

TSMC 2026 OIP Ecosystem Forum Summary
by Daniel Nenni on 10-09-2026 at 8:00 am

TSMC Ecosystem Forum Summary

TSMC’s 2026 Open Innovation Platform Forum presented artificial intelligence as the force reshaping semiconductor design. Its central argument is that faster chips will require progress across the whole system: logic, memory, packaging, interconnects, power delivery and design methods. TSMC places its partner ecosystem… Read More


CASPA CEO Summit and Why it Matters

CASPA CEO Summit and Why it Matters
by Daniel Nenni on 10-09-2026 at 6:00 am

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It’s an honor to attend events like this as a guest, and even more so as a speaker. On Friday at 3:30 p.m., I’ll be moderating a panel with the CEOs of three of the hottest AI startups. I definitely have a few questions ready for them!  My beautiful wife and I will also be at the banquet. I hope to see you there!

The CASPA CEO Summit arrives … Read More


Data Center Energy Trends Force a Rethink of Chip Power Delivery

Data Center Energy Trends Force a Rethink of Chip Power Delivery
by Daniel Nenni on 10-08-2026 at 10:00 am

Data Center Energy Trends Force a Rethink of Chip Power Delivery

Intel Foundry published a two article series on chip power delivery that are worth reading. Here is a quick summary:

Artificial intelligence is changing the requirements for semiconductor innovation. Faster transistors and denser packaging remain essential, but their benefits increasingly depend on another engineering… Read More


WEBINAR: The Convergence of Edge Accelerators

WEBINAR: The Convergence of Edge Accelerators
by Daniel Nenni on 10-08-2026 at 8:00 am

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The rapid growth of AI at the edge is forcing SoC architects to rethink traditional processor designs. Dedicated NPUs deliver impressive performance for today’s models, but evolving AI workloads, increasing system complexity and growing pressure on power and silicon budgets are exposing the limitations of fixed-function… Read More


The silent killer of analog reliability: Why SPICE misses floating net

The silent killer of analog reliability: Why SPICE misses floating net
by Admin on 10-08-2026 at 6:00 am

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By Bhanu Pandey

The semiconductor industry is currently facing a significant challenge in functional verification. According to the most recent Wilson Research Group / Siemens EDA Functional Verification Study, first-silicon success rates have hit a historic low, with nearly 68% of designs requiring two or more spins. While… Read More


From Blueprint to Production: How Rambus Brings Commercial-Grade Caliptra Security to AI SoCs

From Blueprint to Production: How Rambus Brings Commercial-Grade Caliptra Security to AI SoCs
by Kalar Rajendiran on 10-07-2026 at 10:00 am

CryptoManager Interfaces for Platform Level Security Orchestration

Semiconductor designers today face a critical hurdle: how to smoothly transition from an open-source hardware blueprint to a commercially hardened, production-ready silicon implementation. As semiconductors play an increasingly essential role in powering the AI era, safeguarding these hardware foundations has become… Read More


From Cloud to Silicon: IC-Link and TSMC Open the Door

From Cloud to Silicon: IC-Link and TSMC Open the Door
by Daniel Nenni on 10-07-2026 at 8:00 am

From Cloud to Silicon IC Link and TSMC Open the Door

Access to advanced semiconductor technology involves much more than choosing a process node. Design teams also need computing capacity, compatible tools, secure technology access, and experienced support. IC-Link by imec’s expanded collaboration with TSMC addresses that combination, potentially making sophisticated… Read More


Wilson Survey Signals Need for New Understanding of Verification Success

Wilson Survey Signals Need for New Understanding of Verification Success
by Bernard Murphy on 10-07-2026 at 6:00 am

Siemens Wilson first silicon success

Siemens has again sponsored a Wilson-led survey on the state of (functional) verification in the industry, and this time Harry Foster (Chief Scientist, Verification at Siemens) has condensed his major takeaways from the report. These are intriguing – particularly an apparent revolutionary change in first-silicon trends.… Read More


Podcast EP372: An Overview of Some Important New Sessions at Semicon West with Julie Rogers

Podcast EP372: An Overview of Some Important New Sessions at Semicon West with Julie Rogers
by Daniel Nenni on 10-07-2026 at 4:00 am

Daniel is joined by Julie Rogers, Executive Director, ESD Alliance. Julie brings deep expertise in industry collaboration, technical conferences, and executive engagement. She brings more than 30 years of experience driving growth, visibility, and alignment across complex, highly technical markets. She is widely recognized… Read More


Beyond the Die: Verifying the Connected Chip

Beyond the Die: Verifying the Connected Chip
by Daniel Nenni on 10-06-2026 at 10:00 am

Efficient, Scalable Methodology for Reliability and ESD Verification of Complex 3D IC CoWoS Systems

One of the standout presentations at the 2026 TSMC OIP Forum highlighted a collaboration between Siemens EDA, Marvell, and TSMC. I always appreciate EDA presentations that bring together customer and foundry perspectives, and this one did not disappoint. We follow 3D IC technology closely and have published more than 150 blogs… Read More