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Semiconductor Expert Forum

Podcast EP321: An Overview of Soitec’s Worldwide Leadership in Engineered Substrates with Steve Babureck

Podcast EP321: An Overview of Soitec’s Worldwide Leadership in Engineered Substrates with Steve Babureck
by Daniel Nenni on 12-05-2025 at 10:00 am
Categories: Foundries, Soitec

Daniel is joined by Steve Babureck, executive vice president of strategy and president of Soitec USA. He joined the company in 2011 and held various positions including head of the finance department of the solar business in the United States, head of strategic marketing, and head of Group investor Relations in San Diego and Singapore.… Read More

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ClockEdge Delivers Precision, Visibility and Control for Advanced Node Clock Networks

ClockEdge Delivers Precision, Visibility and Control for Advanced Node Clock Networks
by Mike Gianfagna on 12-05-2025 at 6:00 am
Categories: ClockEdge, EDA

ClockEdge Delivers Precision, Visibility and Control for Advanced Node Clock Networks

At advanced nodes, the clock is no longer just another signal. It is the most critical and sensitive electrical network on the chip, and the difference between meeting performance targets and missing the tape-out often comes down to a few picoseconds, buried deep inside the clock distribution network. Yet many design teams still… Read More

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WEBINAR: Defacto’s SoC Compiler AI: Democratizing SoC Design with Human Language

WEBINAR: Defacto’s SoC Compiler AI: Democratizing SoC Design with Human Language
by Daniel Nenni on 12-04-2025 at 10:00 am
Categories: Defacto Technologies, EDA, Events

webinar square2025 (1)

Modern chip design has reached unprecedented levels of complexity. Today’s System-on-Chip (SoC) designs integrate multiple processors, complex memory hierarchies, sophisticated interconnects, and much more. All requiring orchestration using complex EDA tool flows. Months are routinely lost to configuration… Read More

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An Assistant to Ease Your Transition to PSS

An Assistant to Ease Your Transition to PSS
by Bernard Murphy on 12-04-2025 at 6:00 am
Categories: AI, EDA, Siemens EDA

PSS Assistant min

At times it has seemed like any development in EDA had to build a GenAI app that would catch the attention of Wall Street. Now I see more attention to GenAI being used for less glamorous but eminently more practical advances. This recent white paper from Siemens on how to help verification engineers get up to speed faster with PSS is … Read More

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Accelerating NPI with Deep Data: From First Silicon to Volume

Accelerating NPI with Deep Data: From First Silicon to Volume
by Kalar Rajendiran on 12-03-2025 at 10:00 am
Categories: Analytics, EDA, IP, proteanTecs

proteanTecs Multi Pillar Technology

For decades, semiconductor teams have relied on traditional methods such as corner-based analysis, surrogate monitors, and population-level statistical screening for post-silicon validation. These methods served well when variability was modest, and timing paths behaved predictably. However, today’s advanced nodes… Read More

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We Need to Turn Specs into Oracles for Agentic Verification

We Need to Turn Specs into Oracles for Agentic Verification
by Bernard Murphy on 12-03-2025 at 6:00 am
Categories: AI, EDA, Moores Lab (AI)

Spec as an oracle min

The natural language understanding now possible in LLMs has raised interest in using specs as a direct reference for test generation, to eliminate need for intermediate and fallible human translation. Sadly, specs today are not an infallible source of truth for multiple reasons. I am grateful to Shelly Henry (CEO of MooresLab)… Read More

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Accelerating SRAM Design Cycles: MediaTek’s Adoption of Siemens EDA’s Additive AI Technology at TSMC OIP 2025

Accelerating SRAM Design Cycles: MediaTek’s Adoption of Siemens EDA’s Additive AI Technology at TSMC OIP 2025
by Daniel Nenni on 12-02-2025 at 10:00 am
Categories: EDA, Events, Siemens EDA, TSMC

Siemens MediaTek TSMC OIP 2025

In the competitive vertical of mobile System-on-Chip development, SRAM plays a pivotal role, occupying nearly 40% of chip area and directly impacting yield and performance. The presentation “Accelerating SRAM Design Cycles With Additive AI Technology,” co-delivered by Mohamed Atoua of Siemens EDA and Deepesh… Read More

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United Micro Technology and Ceva Collaborate for 5G RedCap SoC and Why it Matters

United Micro Technology and Ceva Collaborate for 5G RedCap SoC and Why it Matters
by Daniel Nenni on 12-02-2025 at 6:00 am
Categories: Automotive, Ceva, IP

CEVA United Micro 5G

In the ultra competitive automotive technology race the integration of advanced connectivity is no longer a luxury but a necessity. As vehicles transition from isolated machines to intelligent nodes in a vast ecosystem, seamless, reliable communication becomes paramount. On November 11, 2025, Ceva, Inc., a leading licensor… Read More

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Transforming Functional Verification through Intelligence

Transforming Functional Verification through Intelligence
by Daniel Payne on 12-01-2025 at 10:00 am
Categories: EDA, Siemens EDA

Wilson Research Group, project schedule min

SoC projects are running behind schedule as design and verification complexity has increased dramatically, so just adding more engineers, more tests and more compute aren’t the answer. The time is ripe to consider smarter ways to improve verification efficiency. The added complexity of multiple embedded processors, multiple… Read More

Podcast EP320: The Emerging Field of Quantum Technology and the Upcoming Q2B Event with Peter Olcott

Podcast EP320: The Emerging Field of Quantum Technology and the Upcoming Q2B Event with Peter Olcott
by Daniel Nenni on 12-01-2025 at 9:00 am
Categories: Events, Semiconductor Services, Silicon Catalyst

Daniel is joined by Peter Olcott, Deeptech Principal at First Spark Ventures specializing in early-stage investments. His background encompasses over 20 years of experience in electrical engineering, software engineering, algorithm design, combined hardware-software robotic devices, and novel innovations in biomedical… Read More