WEBINAR: Revolutionizing Electrical Verification in IC DesignIn the complex world of IC design, electrical…Read More
Silicon Catalyst on the Road to $1 Trillion IndustryThere were quite a few announcements at the…Read More
Hierarchically defining bump and pin regions overcomes 3D IC complexityBy Todd Burkholder and Per Viklund, Siemens EDA…Read More
CDC Verification for Safety-Critical Designs – What You Need to KnowVerification is always a top priority for any…Read More
Ceva Unleashes Wi-Fi 7 Pulse: Awakening Instant AI Brains in IoT and Physical RobotsIn the rapidly evolving landscape of connected devices,…Read More
As they have done for the last few years, Atrenta held its fifth annual user group meeting at the Shin Yokohama Kokusai Hotel on September 13. The attendees are a mixture of customers and other interested members of the semiconductor supply chain. There were nearly 90 people there representing 48 different companies in Japan.
The… Read More
At this year’s DAC, I spoke with several friends at Cadence. I got the distinct impression that something at Cadence had changed. There was a sense of pride and accomplishment that it seems to me had drifted away over the years. Now employees were speaking with true conviction about the accomplishments of the product development… Read More
Electronic Design Automation Software and Semiconductor Intellectual Property are not so much the tail that wags the dog, rather they are like the heart of an elephant, tiny in comparison but without which there is no elephant. There is no doubt that EDA and IP have been key enablers of the semiconductor industry for the past 50 years… Read More
From chip IP vendor ARM Holdings to semiconductor foundry Taiwan Semiconductor, there have been many winners from the mobile device revolution that was sparked by Apple’s introduction of the iPhone. However, while these big-ticket names get all the fame and glory, the electronic design automation space (“EDA” for short) is … Read More
My background includes transistor-level IC design, so I take delight in talking with engineers like Dr. Lanny Lewyn that are still practicing the art and science of analog IC design. Dr. Lewynis a Life Senior Member of the IEEE and has a consulting business. If you live in Santa Clara, then consider attending a live seminar on October… Read More
The 5[SUP]th[/SUP] annual TSMC OIP Forum was last week and thankfully there were no surprises with the exception of how many people asked me who I think will be the next TSMC CEO. Certainly I have no idea but I would be happy to use my incredible powers of deductive reasoning to determine who it will be.
The TSMC Open Innovation Platform®… Read More
More details are now available for the EDA 50[SUP]th[/SUP] anniversary event on October 16[SUP]th[/SUP]. If you have not been to the museum lately this is a must see event as it is all new. Definitely check out the auction items! Just do not bid against me or it will get very expensive for one of us. I’m watching Storage Wars reruns so… Read More
VIPs (Verification IPs) are really important in this complex world of SoCs which involve various IPs, interfaces and continuously evolving protocols and standards, thus making the task of verifying an overall system extremely challenging. And the verification must be done in minimum possible run-time and memory consumption.… Read More
Standard cell optimization is an important problem, because the speed, power, and area of cells has a direct impact speed, power, and area of the whole chip. Typically, standard cell optimization been done with simple in-house local-optimizer scripts. However, these optimizers have had several flaws: they don’t properly capture… Read More
Analog and mixed-signal ICs are tougher to design and verify compared to digital, so if you want to learn more about best practices from actual AMS engineers then consider attending a summitthat is sponsored by Cadence Design Systems next Thursday, October 10th in San Jose from 8:00AM until 6:30PM.
They’ve lined up an interesting… Read More
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