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Securing UALink in AI clusters with UALinkSec-compliant IP

Securing UALink in AI clusters with UALinkSec-compliant IP
by Don Dingee on 03-24-2026 at 10:00 am

UALinkSec 200 Security Module block diagram

A classic networking problem is securing connections with encrypted data, but implementing strong encryption algorithms at wire speeds can limit performance. However, introducing blazing-fast connectivity without an encryption strategy leaves systems vulnerable. The architects in the UALink Consortium, including … Read More


GTC 2026: Agentic AI for Semiconductor Design and Manufacturing

GTC 2026: Agentic AI for Semiconductor Design and Manufacturing
by Daniel Nenni on 03-24-2026 at 8:00 am

Agentic AI is emerging as a transformative paradigm in semiconductor design and manufacturing, driven by the exponential growth in data, system complexity, and performance demands. Modern semiconductor fabs generate massive volumes of heterogeneous data at unprecedented velocity. For instance, a single minute of operation

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Trust in Verification with AI

Trust in Verification with AI
by Bernard Murphy on 03-24-2026 at 6:00 am

Uncharted waters

These are stressful times in functional verification. We are being pushed to more aggressively embrace AI-based automation, knowing we will continue to be held accountable for quality of results. Verification misses could upend careers, maybe enterprises. It is tempting to believe that sanity will prevail and we will ultimately… Read More


Scaling Multi-Die Connectivity: Automated Routing for High-Speed Interfaces

Scaling Multi-Die Connectivity: Automated Routing for High-Speed Interfaces
by Kalar Rajendiran on 03-23-2026 at 10:00 am

Bump maps for HBM PHY and HBM memory

This article concludes the three-part series examining key methodologies required for successful multi-die design. The first article Reducing Risk Early: Multi-Die Design Feasibility Exploration focused on feasibility exploration and early architectural validation, while the second article Building the InterconnectRead More


Beyond Moore’s Law: High NA EUV Lithography Redefines Advanced Chip Manufacturing

Beyond Moore’s Law: High NA EUV Lithography Redefines Advanced Chip Manufacturing
by Daniel Nenni on 03-23-2026 at 8:00 am

DSC00975

The imec installation of the ASML EXE:5200 High Numerical Aperture (High NA) extreme ultraviolet (EUV) lithography system at imec represents a pivotal advancement in semiconductor manufacturing and research. This system, installed in imec’s 300 mm cleanroom in Leuven, Belgium, introduces unprecedented lithographic resolution… Read More


Arteris Highlights a Path to Scalable Multi-Die Systems at the Chiplet Summit

Arteris Highlights a Path to Scalable Multi-Die Systems at the Chiplet Summit
by Mike Gianfagna on 03-23-2026 at 6:00 am

Arteris Highlights a Path to Scalable Multi Die Systems at the Chiplet Summit

At the recent Chiplet Summit, presentations, discussions and general participation could be broken down into a few broad categories. There were presentations of actual chiplet designs, either as building blocks or end products. There were presentations regarding design tools and methodologies to support and accelerate … Read More


CEO Interview with Moti Margalit of SonicEdge

CEO Interview with Moti Margalit of SonicEdge
by Daniel Nenni on 03-22-2026 at 2:00 pm

SonicEdge Moti Margalit

Moti Margalit is the CEO and co-founder of SonicEdge, a deep-tech pioneer reinventing sound through ultrasonic modulation – unlocking smaller, vibration-free speakers with studio-quality audio.

With a background in lasers and electro-optics, Moti transitioned from technologist to inventor. His career spans 150+ patents… Read More


Podcast EP336: How Quadric is Enabling Dramatic Improvements in Edge AI with Veer Kheterpal

Podcast EP336: How Quadric is Enabling Dramatic Improvements in Edge AI with Veer Kheterpal
by Daniel Nenni on 03-20-2026 at 10:00 am

Daniel is joined by Dr. Veer Kheterpal. Veer has founded three technology companies and possesses full-stack expertise spanning software to silicon across edge and datacenter applications. Currently, he is the CEO & co-founder of Quadric, a semiconductor IP licensing company that delivers the blueprints for efficient,… Read More


Captain America: Can Elon Musk Save America’s Chip Manufacturing Industry?

Captain America: Can Elon Musk Save America’s Chip Manufacturing Industry?
by Jonah McLeod on 03-20-2026 at 6:00 am

Elon Musk Lip Bu Tan Wafer Deal

Intel has posted three consecutive years of falling revenue and an $18.76 billion loss in 2024 alone—and the U.S. government has handed it tens of billions of dollars to fix the problem. The government money isn’t fixing the real issue, which isn’t technical. It’s cultural. Intel got slow, political, and risk-averse—the… Read More


WEBINAR: Reclaiming Clock Margin at 3nm and Below

WEBINAR: Reclaiming Clock Margin at 3nm and Below
by Daniel Nenni on 03-19-2026 at 2:00 pm

Webinar Blog Image Reclaiming Clock Margin

At 3nm and below, clock networks have quietly become the dominant limiter of SoC power, performance, and yield. Yet most advanced-node designs still rely on abstraction-based signoff methodologies developed when voltage headroom was generous and interconnect effects were secondary.

That assumption no longer holds

As supply… Read More