The Sky’s the Limit: SiFive’s BigSky Brings RISC-V to the DatacenterSiFive is bringing RISC-V closer to mainstream datacenter…Read More
What Hot Chips 2026 Tells Us About What Silicon Valley Is Actually BuildingHere’s what the presentations selected for the 2026…Read More
Reducing EUV Exposure Dose Through Underlayer EngineeringExtreme-ultraviolet lithography is essential for manufacturing advanced semiconductor…Read More
The Twelve-Month Rule Does Not Describe a New FabBy Nikhil Shah Capital spending is often treated…Read More
Akhilesh Kumar & Krishnakanth Sistla, Intel
Diamond Rapids is Intel’s next-generation Xeon processor, designed around the proposition that hyperscale performance increasingly depends on moving, processing, and protecting data as efficiently as executing instructions. The architecture replaces the conventional… Read More
When Lindu Krishna joined Axiomise after a career break, she wasn’t just relearning technical concepts – she was rebuilding her confidence, redefining what it means to be a woman engineer and quietly becoming the person who can take ownership of complex formal verification blocks. Backed by a culture where nobody sits … Read More
During my time at DAC 2026 I felt like I was attending two events. One was the traditional DAC where approaches to designing complex chips using the best tools and methodologies were the focus. There was another focus for the conference. This one was like the traditional DAC with an important difference. Here, the discussion centered… Read More
The reported move of Amit Gupta, Jeff Dyck, and Ryan Silk from Siemens EDA to Synopsys matters because this is more than a routine transfer of experienced executives and engineers. Together, the three represent a concentrated body of expertise in applying artificial intelligence to semiconductor design—one of the most strategically… Read More
Lance Hacking, Intel
Intel Core Series 3, code-named Wildcat Lake, is a mainstream client system-on-chip derived from the Panther Lake-based Core Ultra Series 3 architecture. Its design objective is not maximum feature density, but broad deployment of current-generation CPU, graphics, AI, memory, security, and connectivity… Read More
In advanced packaging, warpage is rarely a modeling problem. It is a timing problem.
JOHN BRUGGEMAN
By the time many advanced packages undergo high-fidelity thermo-mechanical analysis, a long chain of decisions has already been made. Stackup. Materials. Die placement. Package architecture. Each decision constrains the … Read More
Signoff-quality design tools are mandatory for signoff, though not so good for early design exploration. Signoff demands high accuracy in design description and high precision in analysis. The first requirement can’t be met early in design where architecture decisions are still in flux, and the second depends on very detailed… Read More
Modern ASIC, SoC, CPU, and GPU development depends on verification processes that detect subtle functional defects before tapeout. SystemVerilog Assertions (SVA) are particularly important because they encode temporal design intent: how signals, states, and transactions must behave across clock cycles. Unlike conventional… Read More
RISC-V has evolved from a Berkeley research architecture into a global instruction-set standard spanning embedded controllers, application processors, accelerators, and emerging servers. Its defining technical characteristic is not merely openness, but disciplined modularity. Four ratified base ISAs—RV32I, RV64I,… Read More
Artificial intelligence performance is increasingly constrained by memory rather than arithmetic throughput. Scaling laws show that model quality improves when parameter count, training data, and compute grow together, but this balance fails when processors cannot obtain operands quickly enough. Contemporary accelerators… Read More
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