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RISC-V: From Niche Architecture to Strategic Foundation

RISC-V: From Niche Architecture to Strategic Foundation
by Kalar Rajendiran on 05-07-2026 at 10:00 am

The RISC V Inflection Point

At the recent RISC-V Now by Andes conference, Aion Silicon’s presentation made one thing clear: RISC-V is no longer an emerging alternative but rather rapidly becoming foundational to modern silicon design. This conviction is not theoretical says Oliver Jones, CEO of Aion Silicon, who gave the talk. It is grounded in Aion Silicon’s… Read More


Bringing mathematical rigour in the world of hardware – a journey into Formal Verification

Bringing mathematical rigour in the world of hardware – a journey into Formal Verification
by Daniel Nenni on 05-07-2026 at 6:00 am

Robert Simpson picture

This interview presents the first steps of Robert Simpson (R.S.), a Maths graduate who found an unexpected, but natural home in Formal Verification (FV) at Axiomise. Drawn by a desire to apply rigorous logic to real-world problems, he shares how abstract mathematical thinking translates into ensuring hardware correctness … Read More


The Great Divide: A Tale of Three Hardware Emulation Architectures

The Great Divide: A Tale of Three Hardware Emulation Architectures
by Lauro Rizzatti on 05-06-2026 at 10:00 am

A Tale of Three Hardware Emulation Architectures

Hardware emulation arose as a necessity out of the needs of the eighties. By the mid-1980s, semiconductor designs had outgrown the practical limits of gate-level simulation. Gate-level simulation delivered accuracy, but at glacial pace; silicon prototypes performed at real-speed but arrived far too late. The industry needed… Read More


A Different Angle on Co-Simulation for Systems

A Different Angle on Co-Simulation for Systems
by Bernard Murphy on 05-06-2026 at 6:00 am

FMI use cases

Co-simulation, two or more simulations running concurrently in some manner, is not a new idea. I have written before about multiphysics systems able to model thermal, stress, CFD and other factors simultaneously. I just read a white paper from Siemens based on a different method, using an open standard called the Functional Mockup… Read More


Synopsys and TSMC Deepen AI Design Alliance: What It Means

Synopsys and TSMC Deepen AI Design Alliance: What It Means
by Kalar Rajendiran on 05-05-2026 at 10:00 am

Synopsys Powering the next generation of AI

A recent announcement from Synopsys signals a meaningful escalation in the race to build next-generation AI hardware. The expanded collaboration between Synopsys and TSMC brings together silicon-proven IP, AI-driven design tools, and cutting-edge manufacturing processes in a tightly integrated effort to accelerate high-performance… Read More


Siemens U2U 3D IC Design and Verification Panel

Siemens U2U 3D IC Design and Verification Panel
by Daniel Nenni on 05-05-2026 at 6:00 am

IMG 1201

Given the success of the event in Silicon Valley last week, I would expect the Siemens U2U event in Munich to be even bigger. In my experience this has been the best user driven event in 2026 with the deepest customer content. EDA has always been a customer driven industry and it is good to see us recognize that from time to time. Kalar … Read More


Connecting the Dots: Why RISC-V System Design Is Entering a New Era

Connecting the Dots: Why RISC-V System Design Is Entering a New Era
by Kalar Rajendiran on 05-04-2026 at 10:00 am

Andes x Arteris Pre Verified and Silicon Proven SoC Integration

At the recent RISC-V Now event hosted by Andes, the discussion underscored the fact that RISC-V is no longer just about instruction set architecture advantages or customizable cores. The real focus has moved up the stack to system-level design. This is where connectivity, integration, and security define whether an innovation… Read More


Rethinking ECAD IT Infrastructure: From Fragmentation to an Engineering Platform

Rethinking ECAD IT Infrastructure: From Fragmentation to an Engineering Platform
by Kalar Rajendiran on 05-04-2026 at 6:00 am

The semiconductor industry is entering a new phase of complexity. Advanced nodes, heterogeneous integration, and AI-driven design workflows are placing unprecedented demands on engineering teams. While much of the focus remains on tools and methodologies, an equally critical constraint is emerging beneath the surface:… Read More


CEO Interview with Geoffrey Rodgers of Chameleon Semiconductor

CEO Interview with Geoffrey Rodgers of Chameleon Semiconductor
by Daniel Nenni on 05-03-2026 at 2:00 pm

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Geoffrey Rodgers spent most of his career at the intersection of semiconductor technology and go-to-market execution, with a focus on scaling businesses and bringing complex solutions to market. He previously led the Analog Go-To-Market motion at Synopsys following the acquisition of Analog Design Automation and held leadership… Read More


Bronco AI Webinar: Full-Chip SoC Debug in 15 Minutes

Bronco AI Webinar: Full-Chip SoC Debug in 15 Minutes
by Daniel Nenni on 05-01-2026 at 10:00 am

BroncoBlogPostDetective

A single bug on a full-chip SoC can pull engineers off roadmap work for days or even weeks. It involves massive waveforms, thousands of files of RTL and UVM, and dense specs that aren’t always perfect. Finding these bugs have always been a matter of engineer-hours and how well knowledge diffuses through the organization.

Bronco … Read More