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The Grand Folly of India’s Foundry Plans, Part 2

The Grand Folly of India’s Foundry Plans, Part 2
by Peter Gasperini on 08-04-2014 at 8:00 am

Image Source: Wikipedia

Authors: Pete Gasperini & Abhijit Athavale

The first article on this topic, published here on Semiwiki on July 6[SUP]th[/SUP], addressed New Delhi’s proposal to subsidize the construction of two silicon fabs – one in 22nm, the other in 28nm – in order to stimulate India’s high tech sector and reduce its dependence on foreign technology imports. The argument against this detailed multiple technical and economic factors which negated the purported benefits of the initiative and proposed alternative courses of action.

Defenders of the fab subsidy program have subsequently raised a new issue to bolster their side of the argument. In late 2012, an FPGA sold by Microsemi and extensively used in systems employed by the US military was discovered by Cambridge researchers to have a hardware Trojan. This backdoor, deliberately inserted by designers at Microsemi, was accessible thru the chip’s JTAG pins and permitted a 3[SUP]rd[/SUP] party to remotely reconfigure the device, access its code and even disable it.

Fab proponents are concerned that chip designs from Indian companies could be sabotaged in foreign foundries and have circuitry covertly embedded which would allow spies and saboteurs to steal commercial information or attack private or military systems employing those chips. The question is: how realistic is such a possibility?

A sculptor wields
The chisel, and the stricken marble grows
To beauty. –
William Cullen Bryant

As everyone here is well aware, when a chip design team develops a new product, they don’t just write some code, throw it at a software tool, press “Enter” and have a functional chip pop out from a 3D printer. The process involves ESL abstractions, Verilog descriptions, an expensive portfolio of EDA software whose complexity is such that team members need to specialize in its particular tools, a library of physical, electrical and functional models of increasing sophistication applied in multiple stages of the design flow, and multi-corner PVT characterization to ensure designs yield and perform per specification to any allowed combination of process node, operating temperature and application voltage variances. There are intricately detailed methodologies for timing closure, functional verification, DFT, DFM, power optimization, signal integrity, hierarchical design, clock tree integration, voltage islands, IP integration, timing domains, place & route, mixed signal and/or analog block integration and so on. All thru the development cycle, things are repeatedly tested, verified, analyzed, optimized and otherwise shaked & baked.

It takes 15-18 months of labor by 20-40 seasoned engineers to do this work – time spent using their accumulated skills to craft, sculpt and ultimately realize a functional and timing equilibrium as close to perfection as they can make it. As a consequence, any disturbance to the design is guaranteed to be catastrophic, affecting timing, layout, functionality, yield, power and interconnect.

When one takes into account that only the original development team has all the correct tools, models, code and verification suite, it becomes obvious that a third party at a foundry simply cannot meddle with a design database and successfully insert extra gates for a hardware backdoor. The design will be compromised and even the most ingenious engineering team will simply not be able to integrate the Trojan and restore the design to its original functional and timing envelope without years of reverse engineering work. By the time such an effort is completed, all the organizations that were targets of the chip saboteurs will already have bought systems with untouched, original chips in them.

The truth of the matter is that India doesn’t need New Delhi to step into its technology industry to help, but would actually benefit more if the central government did less. The chip security issue, along with ideas for New Delhi to do other, more beneficial things that will advance India’s high tech sector and improve its trade balance, are discussed in greater depth at

Also Read: Semiconductor Manufacturing in India?

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