On Tuesday morning I headed off to the Mentorbooth at DACfor an update on their Custom IC Design and AMS Simulation/Verification tools, Christopher Cone was the presenter. Also in the room were Jay Madiraju, and Mick from Berkeley DA.… Read More
FDSOI Target Applications Are…
Not PC segment, not necessarily Application Processor for Mobile, despite the power efficiency advantage versus a bulk technology. After several weeks filled by very animated and controversial discussion about FD-SOI cost, thanks to Semiwiki bloggers and readers, it seems interesting to elevate the debate and try to figure… Read More
eSilicon and the Ten Minute Quote
One of the challenges in bringing a design into production is getting a quote that includes all the various stages of the process. The quote cycle typically takes a couple of weeks. It is also pretty wasteful. A typical design might be quoted by 3 manufacturers and so 2 out of 3 quotes are wasted expense because the design is lost to a … Read More
It’s not a fiction, it’s about to turn into reality
Often I used to wonder why a search engine company would invest so heavily and indulge into stuff like smartphones, home automation devices, servers and many other exotic, innovative things they are doing internally and externally. But when I connect the dots, I find that this company in on certain massive missions which, if accomplished… Read More
How to Beat a New Entrant with Superior EDA tool
How to handle a new entrant with superior product quality is a point of worried to all EDA companies. Due to continuous research happenings and relatively lower investment requirement new and new EDA start-ups are coming in EDA domains regularly. In several situations, these start-ups offer product of superior quality in terms… Read More
IO Design Optimization Flow for Reliability in 28nm
User group meetings are a rich source of information for IC designers because they have actual designers talking about how they used EDA tools in their methodology to achieve a goal. Engineers at STMicroelectronicspresented at a MunEDAUser Group on the topic: I/O Design Optimization Flow For Reliability In Advanced CMOS Nodes.… Read More
Making IP Reuse and SoC Integration Easier
The last graphics chip that I worked on at Intel was functionally simulated with only a tiny display size of 16×16 pixels, because that size allowed a complete regression test to be simulated overnight. Our team designed three major IP blocks: Display Processor, Graphics Processor and Bus Interface Unit. We wanted to also… Read More
Ensuring ESD Integrity
Electro Static Discharge (ESD) is a fact of life for IC designs and has been ever since electronics were first created and then started failing because of sudden, large currents flowing through the design caused by human, processing or machine contact. It’s just too expensive to layout an IC today, fabricate it, test for … Read More
How Much Power to Allocate to IoT Connectivity?
Ensigma is in fact the low-power radio processing unit (RPU) architecture, completing Imagination Technologies (IMG) port-folio, the well-known graphic processing unit (GPU) PowerVR family and MIPS CPU core products. If we take a look at the block diagram “Ensigma Series4 Explorer RPU”, we can easily identifies the Radio … Read More
EUV Pellicles
Shakespeare reckoned that a man went through seven stages in his life.All the world’s a stage, And all the men and women merely players. They have their exits and their entrances, And one man in his time plays many parts, His acts being seven ages.
Well, an EUV mask seems to only go through three main stages:
[LIST=1]
Real men have fabs!