I’ve been following the evolution of the verification space for a very long time including several stints consulting to formal verification companies. It has always been interesting to me to see how so many diverse verification techniques emerge and been used, but without much unification of the approaches. With the emergence… Read More
The use of safety-centric logic design techniques for automotive applications is now widely appreciated, but did you know that similar methods are gaining traction in the design of enterprise-level SSD controllers? In the never-ending optimization of datacenters, a lot attention is being paid to smart storage, offloading… Read More
On Monday, July 8th Imec held a technology forum ahead of Semicon West. I saw the papers presented and interviewed three of the authors. The following is a summary of what I feel are the keys points of their research.
Arnaud Furnemont’s talk was titled “From Technology Scaling to System Optimization”. Simple 2D … Read More
The “20 Questions with John East” series continues
In 1973 plus or minus a year or so I was working as a supervising engineer in one of the bipolar digital product groups. My boss was a man named Jerry Secrest. He was a great boss – he taught me most of what I knew about ICs in my youth. Jerry had responsibility for a product line. That… Read More
It’s been more than two years since I started the AI chip list. We saw a lot of news about AI chips from tech giants, IC/IP vendors and a huge number of startups. Now I have a new “AI Chip Landscape” infographic and dozens of AI chip related articles (in Chinses, sorry about that :p).
At this moment, I’d like… Read More
I came across a report on the 100 most promising AI start-ups. The report claimed that CBInsights had “selected the 100 most promising AI start-ups from a pool of 3K+ companies based on several factors …” Wait, what … 3K+ companies!?!? This was a stunning reminder of the sheer magnitude of what is shaping up to be a veritable tsunami… Read More
The pace of Moore’s Law scaling for monolithic integrated circuit density has abated, due to a combination of fundamental technical challenges and financial considerations. Yet, from an architectural perspective, the diversity in end product requirements continues to grow. New heterogeneous processing units are being… Read More
In the realm of ESD protection, Charged Device Model (CDM) is becoming the biggest challenge. Of course, Human Body Model (HBM) is still essential, and needs to be used when verifying chips. However, a number of factors are raising the potential losses that CDM events can cause relative to HBM. These factors fall into two categories:… Read More
In the early days of chip design circa 1970’s the engineers would write logic equations, then manually reduce that logic using Karnaugh Maps. Next, we had the first generation of logic synthesis in the early 1980’s, which read in a gate-level netlist, performed logic reduction, then output a smaller gate-level netlist.… Read More
Several years ago, I was a consultant to a company called Gauda, Inc. I enjoyed working with Gauda as the technology was interesting. On June 3, 2014, Gauda, Inc. was acquired by D2S, Inc. so their technology lives on. Gauda was focused on optical proximity correction (OPC) and optical proximity verification solutions utilizing… Read More