David Tester is the VP of Engineering at Mach42, with 30 years of experience in semiconductor development, engineering leadership, and business growth. As Chief Engineer at EnSilica, he helped transform the company from a design consultancy into a publicly listed fabless semiconductor business, scaling the organisation … Read More
How Allegro MicroSystems Increased OEE by Several Percentage Points with yieldHUB LiveAllegro MicroSystems’ experience with yieldHUB Live shows how…Read More
Interview with Sweta Gupta, VP of Engineering of Analog BitsSweta Gupta is the Vice President of Engineering…Read More
WEBINAR: Porting, Analysing & Optimising AI Models onto Edge GPUsModern AI models are opening up new possibilities…Read More
Using AI for Root Cause Analysis of Simulation FailuresI’ve been working with AMIQ EDA for almost…Read More
Agentic AI accelerates 3D IC engineering for the AI factory eraBy Sudarshan Deo, software R&D Manager for 3D…Read MoreGlass Is Becoming an AI Infrastructure Platform
The value of glass will be determined not by its material properties alone, but by whether it can expand the package architecture window and be realized repeatedly at manufacturing scale.
AI infrastructure is pushing advanced packaging into a regime where the substrate itself increasingly determines what can be built.
As packages… Read More
Ceva and Mobilint Bring Physical AI Closer to Everyday Devices
Physical AI is moving closer to everyday reality, and a new collaboration between Ceva and Mobilint offers an encouraging example of how that progress can reach commercial devices. Mobilint’s REGULUS edge AI System-on-Chip brings together Ceva’s SensPro AI DSP and NeuPro-Nano NPU, marking the first production deployment … Read More
The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival
The philosophy of relying on a single, unified IP stack to lower your total cost of ownership is not a new concept invented just for the AI era. Semiconductor engineering teams have been weighing the trade-offs of piecemeal versus integrated intellectual property sourcing for decades. In previous process generations, veering… Read More
CTO Interview with Taylor Barton of Certus Semiconductor
Taylor Barton is a Lead Analog/Mixed-Signal and I/O IC Design Engineer at Certus Semiconductor, where he has worked since December 2022. He has designed more than 20 silicon-proven I/O and ESD libraries and has led analog and I/O IP projects, including ADC and SerDes designs. Taylor holds B.S. and M.S. degrees in Electrical Engineering… Read More
Generating Chip Subsystems Automatically: A New Answer to Manage Chip Design Complexity
By Defacto Staff
Today’s chips are no longer just processors, they are entire systems. A System-on-Chip (SoC) brings together CPU clusters, accelerators, memories, interconnects and dozens of peripherals, often coming from many different teams and vendors. With AI, high-performance computing and IoT driving demand for … Read More
Reimagining 3D IC Design: From Architecture to Signoff
By Keith Felton, Andras Vass-Varnai and Todd Burkholder, Siemens EDA
The semiconductor industry is undergoing a fundamental transformation. Heterogeneous integration, the practice of combining multiple chiplets and specialized components into a single advanced packaging platform, has emerged as a powerful alternative… Read More
GSA Honors Sanjay Mehrotra as Memory Takes Center Stage in Computing
The Global Semiconductor Alliance will present Micron Technology Chairman and CEO Sanjay Mehrotra with its 2026 Dr. Morris Chang Exemplary Leadership Award, recognizing a career that connects foundational flash memory innovation with the demands of modern computing. The presentation is scheduled for GSA’s Annual Awards… Read More
NIST Sets a Clearer Course for the Post-Quantum Security Transition
NIST’s report, Transition to Post-Quantum Cryptography Standards, gives government agencies and technology suppliers a clearer framework for replacing cryptography vulnerable to future quantum computers. Its significance extends beyond selecting algorithms: it connects security priorities, application requirements… Read More
CTO Interview with Ed Plowman of Imagination Technologies
Ed Plowman is Chief Technology Officer at Imagination Technologies, where he leads technology strategy, advanced architecture research and long-term innovation initiatives. He focuses on the convergence of graphics, compute and artificial intelligence, helping shape the next generation of efficient and adaptable computing… Read More


The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival