ASIC-to-FPGA Turnkey Prototyping Bundle: A Practical Path to Earlier Hardware ValidationFor ASIC design teams, the gap between RTL…Read More
Security by Design: Arteris Expands Its Partnership with ArmArteris has expanded its partnership with Arm to…Read More
How early symmetry validation eliminates costly late-stage respinsBy Mauli Shah, Product Engineer, Siemens Analog and…Read More
Rethinking Formal Verification in the AI EraBy Kanav Arora, ML Researcher at ChipAgents Most…Read More
CEO Interview with Ann Wu and Akash Levy of SilimateAnn Wu is Co-founder & CEO of Silimate.…Read More
For modern SoC teams, “shift left” no longer means finding a few more RTL bugs before tape-out. It means moving meaningful system validation earlier—far enough left that firmware, operating systems, drivers, applications, and external interfaces can be exercised before first silicon arrives. This change is essential as software… Read More
As artificial intelligence systems become larger and more demanding, memory is becoming one of the most important constraints in server design. Modern AI workloads do not only require powerful GPUs and accelerators; they also require enormous amounts of data to move quickly and efficiently between memory and compute engines.… Read More
I had a chance sit down with James Huang, Director of Engineering at Alchip Technologies, to discuss the company’s recent multi-die packaging achievements and learn about Alchip’s next steps in pushing the boundaries of innovation for next generation AI ASIC.
James is acknowledged as a leading light in advanced node ASICs, based… Read More
Purple was in fashion at the 2026 Design Automation Conference, where Synopsys reinforced its position at the forefront of AI-powered engineering. Under the conference’s “Chips to Systems” theme, the company showcased intelligent, end-to-end technologies designed to help the semiconductor industry manage unprecedented… Read More
Chips&Media WAVE-J is a high-performance JPEG codec intellectual property core designed for advanced imaging systems that require very large image support, high throughput, flexible pixel formats, and integrated pre- and post-processing. It succeeds the CODAJ12V architecture while retaining compatibility with … Read More
Joseph F. Krause is an American materials scientist, entrepreneur, and U.S. Army National Guard veteran. He is the cofounder and CEO of Radical AI, a New York deep-tech startup founded to accelerate the discovery of advanced materials.
Before Radical AI, Krause conducted nanomaterials research at Rice University, worked on… Read More
Chuck McClish is the founder of Lattrex Inc., a fabless semiconductor startup building Kyttar, an asynchronous, clockless reconfigurable processor for real-time signal processing. He spent 15 years at Microchip Technology in chip design and verification, working across RTL design, UVM verification, synthesis, place-and-route,… Read More
Daniel is joined by Nick Kucharewski Senior Vice President and General Manager for Cisco’s silicon development organization. In this role he is responsible for the end-to-end strategy, cross-functional execution, organization alignment, and product roadmap for Silicon One, Cisco’s uniquely scalable and programmable … Read More
For quite a few years, John Cooley has hosted the Troublemaker Panel at DAC. The event consists of a panel of senior executives from the EDA industry. John Cooley asks his readers for “edgy” questions to ask the panelists and on event day, he does just that. Those with complete responses that are backed with real data from real customers… Read More
CoWoS-S and CoWoS-R are two versions of TSMC’s Chip-on-Wafer-on-Substrate advanced packaging platform. Both technologies are designed to combine high-performance processors, chiplets and high-bandwidth memory, or HBM, within a single package. This shortens the electrical connections between computing and memory components,… Read More
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ASML High-NA EUV is Not Ready for High-Volume Production