Designing semiconductor chips has traditionally been costly and controlled by a few major Electronic Design Automation (EDA) vendors—Cadence, Synopsys, and Siemens EDA who dominate with proprietary tools protected by NDAs and restrictive licenses. Fabrication also requires expensive, often export-controlled equipment.… Read More





Chiplets: providing commercially valuable patent protection for modular products
Many products are assembled from components manufactured and distributed separately, and it is important to consider how such products are manufactured when seeking to provide commercially valuable patent protection. This article provides an example in the field of computer chip manufacture.
Chiplets
A system-on-a-chip
Podcast EP304: PQC Standards One Year On: The Semiconductor Industry’s Next Move
Dan is joined by Ben Packman, Chief Strategy Officer of PQShield. Ben leads global expansion through sales and partner growth across multiple vertical markets, alongside taking a lead role in briefing both government and the supply chain on the quantum threat. He has 30 years of experience in technology, health, media, and telecom,… Read More
IMEC’s Advanced Node Yield Model Now Addresses EUV Stochastics
It lays the foundation for the Stochastics Resolution Gap
Chris Mack, the CTO of Fractilia, recently wrote of the “Stochastics Resolution Gap,” which is effectively limiting the manufacturability of EUV despite its ability to reach resolution limits approaching 10 nm in the lab [1,2]. As researchers have inevitably found, … Read More
WEBINAR: Functional ECO Solution for Mixed-Signal ASIC Design
This webinar, in partnership with Easy-Logic Technology, is to address the complexities and challenges associated with functional ECO (Engineering Change Order) in ASIC design, with a particular focus on mixed-signal designs.
The webinar begins by highlighting the critical role of mixed-signal chips in modern applications,… Read More
Taming Concurrency: A New Era of Debugging Multithreaded Code
As modern computing systems evolve toward greater parallelism, multithreaded and distributed architectures have become the norm. While this shift promises increased performance and scalability, it also introduces a fundamental challenge: debugging concurrent code. The elusive nature of race conditions, deadlocks, … Read More
Perforce Webinar: Can You Trust GenAI for Your Next Chip Design?
GenAI is certainly changing the world. Every day there are new innovations in the use of highly trained models to do things that seemed impossible just a short while ago. As GenAI models take on more tasks that used to be the work of humans, there is always a nagging concern about accuracy and bias. Was the data used to train the model … Read More
Weebit Nano Moves into the Mainstream with Customer Adoption
Disruptive technology typically follows a path of research, development, early deployment and finally commercial adoption. Each of these phases are difficult and demanding in different ways. No matter how you measure it, getting to the finish line is a significant milestone for any company. Weebit Nano is disrupting the way… Read More
Everspin CEO Sanjeev Agrawal on Why MRAM Is the Future of Memory
Everspin’s recent fireside chat, moderated by Robert Blum of Lithium Partners, offered a crisp look at how the company is carving out a durable niche in non-volatile memory. CEO Sanjeev Agrawal’s core message was simple: MRAM’s mix of speed, persistence, and robustness lets it masquerade as multiple memory classes, data-logging,… Read More
A Principled AI Path to Spec-Driven Verification
I have seen a flood of verification announcements around directly reading product specs through LLM methods, and from there directly generating test plans and test suite content to drive verification. Conceptually automating this step makes a lot of sense. Carefully interpreting such specs even today is a largely manual task,… Read More
Can RISC-V Help Recast the DPU Race?