SemiWiki 800x100 DAC FSWG

WP_Query Object
(
    [query] => Array
        (
            [paged] => 668
            [page_id] => author/daniel-payne-57-page51.html
        )

    [query_vars] => Array
        (
            [paged] => 668
            [page_id] => 0
            [error] => 
            [m] => 
            [p] => 0
            [post_parent] => 
            [subpost] => 
            [subpost_id] => 
            [attachment] => 
            [attachment_id] => 0
            [name] => 
            [pagename] => 
            [second] => 
            [minute] => 
            [hour] => 
            [day] => 0
            [monthnum] => 0
            [year] => 0
            [w] => 0
            [category_name] => 
            [tag] => 
            [cat] => 
            [tag_id] => 
            [author] => 
            [author_name] => 
            [feed] => 
            [tb] => 
            [meta_key] => 
            [meta_value] => 
            [preview] => 
            [s] => 
            [sentence] => 
            [title] => 
            [fields] => 
            [menu_order] => 
            [embed] => 
            [category__in] => Array
                (
                )

            [category__not_in] => Array
                (
                )

            [category__and] => Array
                (
                )

            [post__in] => Array
                (
                )

            [post__not_in] => Array
                (
                )

            [post_name__in] => Array
                (
                )

            [tag__in] => Array
                (
                )

            [tag__not_in] => Array
                (
                )

            [tag__and] => Array
                (
                )

            [tag_slug__in] => Array
                (
                )

            [tag_slug__and] => Array
                (
                )

            [post_parent__in] => Array
                (
                )

            [post_parent__not_in] => Array
                (
                )

            [author__in] => Array
                (
                )

            [author__not_in] => Array
                (
                )

            [ignore_sticky_posts] => 
            [suppress_filters] => 
            [cache_results] => 
            [update_post_term_cache] => 1
            [lazy_load_term_meta] => 1
            [update_post_meta_cache] => 1
            [post_type] => 
            [posts_per_page] => 10
            [nopaging] => 
            [comments_per_page] => 50
            [no_found_rows] => 
            [order] => DESC
        )

    [tax_query] => WP_Tax_Query Object
        (
            [queries] => Array
                (
                )

            [relation] => AND
            [table_aliases:protected] => Array
                (
                )

            [queried_terms] => Array
                (
                )

            [primary_table] => wp5_posts
            [primary_id_column] => ID
        )

    [meta_query] => WP_Meta_Query Object
        (
            [queries] => Array
                (
                )

            [relation] => 
            [meta_table] => 
            [meta_id_column] => 
            [primary_table] => 
            [primary_id_column] => 
            [table_aliases:protected] => Array
                (
                )

            [clauses:protected] => Array
                (
                )

            [has_or_relation:protected] => 
        )

    [date_query] => 
    [queried_object] => 
    [queried_object_id] => 
    [request] => SELECT SQL_CALC_FOUND_ROWS  wp5_posts.ID FROM wp5_posts  WHERE 1=1  AND wp5_posts.post_type = 'post' AND (wp5_posts.post_status = 'publish' OR wp5_posts.post_status = 'expired' OR wp5_posts.post_status = 'tribe-ea-success' OR wp5_posts.post_status = 'tribe-ea-failed' OR wp5_posts.post_status = 'tribe-ea-schedule' OR wp5_posts.post_status = 'tribe-ea-pending' OR wp5_posts.post_status = 'tribe-ea-draft')  ORDER BY wp5_posts.post_date DESC LIMIT 6670, 10
    [posts] => Array
        (
            [0] => WP_Post Object
                (
                    [ID] => 886
                    [post_author] => 9491
                    [post_date] => 2011-11-29 08:00:00
                    [post_date_gmt] => 2011-11-29 08:00:00
                    [post_content] =>  One of the challenges with today's SoCs is that chip-finishing, putting the final touches to the SoC working at the chip level, stresses layout editors to the limit. Either they run out of capacity to load the entire chip, or they can handle the entire chip but everything is like wading through molasses, it takes an awfully long time to get anything done.

As a result there are a number of chip viewer tools that focus just on being able to load the SoC and very fast to display. The problem with these is that editing capabilities are either non-existent, it is strictly a viewer, or extremely limited.

 Laker's Blitz is a tool that brings the best of both worlds. It can handle extremely large designs and is between 5 and 20 times faster than regular layout editors. However, it has most of the editing features that regular layout editors have since it is built on top of Laker Custom Layout. It has the same user-interface, same basic editing, same in-memory schema, same integration with DRC/LVS, and the same Tcl extensions.

Blitz is optimized for chip-level operations on very large chips, basically reading GDS, editing, and then writing the GDS back out again. The four big tasks it has been optimized for are:

  • Chip-finishing: chip-level review, editing, assembly and debugging
  • IP merging: replacing IP black-boxes with physical layout
  • SoC assembly and review: assemble IP blocks, trace critical nets, verify and fix boundary DRC errors
  • DRC review and repair: chip-level signoff DRC

Of course not every single thing that you can do in Laker Custom Layout is supported, otherwise it would make no sense to have two tools. In particular, Laker Blitz is 64-bit only, it cannot create or modify Pcells and so on. It is focused strictly on the typical tasks done at the chip level with today's advanced technology node SoCs.




 [post_title] => Blitz, blazing fast layout [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => blitz-blazing-fast-layout [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:41:35 [post_modified_gmt] => 2019-06-15 02:41:35 [post_content_filtered] => [post_parent] => 0 [guid] => https://35.226.139.164/uncategorized/886-blitz-blazing-fast-layout/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 1 [filter] => raw ) [1] => WP_Post Object ( [ID] => 884 [post_author] => 20367 [post_date] => 2011-11-29 00:07:00 [post_date_gmt] => 2011-11-29 00:07:00 [post_content] =>  What if Amazon’s new Kindle Fire, priced at $199 and using a sub $10 TI processor, has effectively started the ball rolling towards forcing Intel and AMD to building a Very Low Cost (perhaps even <$10) x86 mobile processor? A recent article entitled “Amazon’s Risky Strategy” explores the ramifications of Amazon selling Kindle Fires at a loss in order to get eyeballs stuck on Amazon’s web pages for longer and thereby increasing sales. The article goes on to speculate that Amazon will sell a Smartphone in the future to further its strategy. Amazon’s sub $200 subsidized hardware model may be like a magnet pulling mobile PC’s into its price range which would have an impact on x86 CPU features, power and price.

Believe it or not, the original 8088 through the 286 were sold at prices that got down below $10 in 1990. The CPU was a minor percentage of the overall PC cost as IBM, Compaq, and others reaped margins that are to dream of today, even higher than Apple’s current margins.

In the summer of 1990, I recall being in a meeting at Intel with representatives of Sharp’s LCD division. They were showing off the first color LCD for notebook PCs. It was a 10” diagonal but one inch thick – only three working samples existed in the world. We asked what they expected to get for it when it was in volume production. They said $2,000. But first they were going to demo it in their own notebook at Comdex in November 1990. They did and it was a hit. Compaq, then the leader in mobiles had just unveiled the first notebook PC with a 10” monochrome screen and a 386SX processor for $5999. It seemed like the tables were turning towards Sharp. Nine months later the story ended as Sharp couldn’t ramp the color LCD in any appreciable volume. They were too early.


In the above example, the 386 SX was perhaps $60 out of a total system price of $6000, or just 1%. Intel discovered in the 1990's that if they could stoke a little competition between PC manufacturers that it could raise CPU ASPs while system prices dropped. Eventually the CPU as a percentage of the end system price would rise to 10-20%. The CPU is the computer. The rise of the Smartphones and tablets has now put a big question mark on the CPU price model. With the Kindle Fire we have a sustainable razor/razorblade business model that will force all “Consumer” based processors to be not just downsized but right-sized. AMD and Intel are not there today.

As many of you know the price driver of x86 CPUs in the 1990's was MHz as PCs attempted to catch up with the demands of the bloated Microsoft O/S and Office applications. Yes, you can throw Adobe in there as a guilty party as well. But recently, in a meeting over coffee with an Apple engineer, I was shown that the kernel of the iOS occupies only 360MB of the iPhone’s 512MB of memory. Pretty lightweight – can I say “DOS like”? Low-end notebooks typically have 2GB to 4GB and Microsoft promises to lighten up Windows 8. It is their way of enabling ARM processors. The bottom line is that x86 processors have to imagine a world where they will be sitting idle or barely running most of the time. What does this mean in terms of features and architecture?

As mentioned in a previous blog, the rise of 10” LCD based netbooks in the downturn of 2008-2009 was based purely on a minimalists need in the midst of an Economic Depression. Their following downfall was not based on the much higher cost Apple iPAD but due to the fact that 14” LCDs had cratered in price. Expect Moore’s Law to continue pushing LCDs down in price. In addition, trends are in place for SSDs to do a number on HDDs, then the game gets interesting. Small formfactor, power-sipping SSDs naturally force other components to come out of their shadows and face their re-architecting. More specifically, the push will be on to reduce enclosure costs, battery capacities, power supply infrastructure, and the processor cooling overhead. All of these can go on a diet once the processor is redesigned for “coolness”.

If AMD or Intel offers a $10 -$20 processor + graphics (APU in AMD terminology) that reduces both Thermal Design Power (TDP) to <5W while consuming much lower power (especially in standby), then the OEM can move consumer PCs towards the Amazon Kindle Fire price. The top speed would be closer to 1Ghz. We would also see smaller on chip caches but a more robust graphics core. Obviously Microsoft has a role here in reducing costs. But this should be part of their grand Cloud strategy.

The net-net of it all is the x86 processor gets to return to its price and power roots of the 1980's but at a higher 5-10% of end system price. I believe Intel and AMD see this, but the cost structures of both companies are built around a much higher ASP model. Given AMD’s current situation, it is likely that they will make the jump first. In either case, ARM suppliers like nVidia, Qualcomm and others with the help of Microsoft and Google are already working on carving out an increasing portion of mobiles under $299 in a profitable manner. This by the way is what Jen Hsun Huang is referring to when he says "Clamshell" devices on Windows 8, a sub category to a Full, legacy compatible mobile PC.


FULL DISCLOSURE: I am Long AAPL and INTC




 [post_title] => Will Amazon’s Kindle Fire Force x86 Processors To Revisit the 1980s? [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => will-amazons-kindle-fire-force-x86-processors-to-revisit-the-1980s [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:41:35 [post_modified_gmt] => 2019-06-15 02:41:35 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/will-amazons-kindle-fire-force-x86-processors-to-revisit-the-1980s.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [2] => WP_Post Object ( [ID] => 885 [post_author] => 3 [post_date] => 2011-11-28 13:11:00 [post_date_gmt] => 2011-11-28 13:11:00 [post_content] => My last IC design at Intel was a Graphics Chip and I developed a layout generator for Programmable Logic Arrays (PLA) that automated the task, so I've always been interested in how to make IC layout more push-button and less polygon pushing. Today I watched a video about HiPer DevGen from Tanner EDA and wanted to share what I learned. This technology came from IC Mask, a Dublin-based services and training company.

HiPer DevGen has a focus on accelerating analog layout while giving the designer control over the process. Analog generators have been developed for:

  • Current Mirrors
  • Differential Pairs
  • Resistor Dividers

Using these layout generators will get you quickly into a layout that is correct by construction and that looks like hand-crafted layout. The layout generators are silicon-aware and use double contacts and vias as appropriate for a given technology node, also taking into account:

  • Linear process gradients
  • Mask misalignment
  • Implant shadowing
  • Shallow Trench Isolation (STI)
  • Length of Diffusion (LOD)
  • Lithography invariance
  • Current flow direction
  • Antenna effect, Vt shift
  • Well Proximity Effect (WPE)

The design flow shown below starts with schematic capture that infers analog structures that will be automated with HiPer DevGen, then the designer uses Schematic Driven Placement and does manual placement adjustments as needed along with automated or manual routing.


Technology setup is done with a GUI and you can type in your layout rules in about 20 minutes for a new process node, or just ask if this is already available for the foundry you've selected:


OpAmp Example
A simple 11 transistor netlist was used that had differential pairs, current mirrors and other transistors:

With Schematic Driven Layout and HiPer DevGen you quickly get a layout with five instances that correspond to your schematic:

In a few minutes you can change the aspect ratio of each layout block and re-position the placement of each block to reach a more optimal layout.


Within 10 minutes the OpAmp has been placed and routed, no mismatches, and with correct-by-construction layout that is DRC and LVS clean:



Using the old-fashioned way of manual analog layout this same design would take you a half day to two full days to get DRC and LVS clean.

Linear Process Gradient
Analog circuits are sensitive to process variations as a function of layout position, so one layout technique to combat this is called Common Centroid. Shown below are devices A and B that have been split up into two areas as Common Centroid where process gradient effects are minimized:



Another benefit of using the Common Centroid layout approach is that it minimizes the effects of mask misalignment:



A current mirror with Common Centroid layout was created by HiPer DevGen using a dialog box in the GUI:


Edge Effects
Polysilicon etch rates depend on how closely spaced poly lines are drawn. Show below is an area where poly edges on the outsides of three devices has been etched more than on the insides of the devices, resulting in performance mismatch:

To minimize edge effects the layout generators place dummy devices on the outside of the active devices:



Complex Current Mirror
Another example of Common Centroid layout was shown with a four-transistor current mirror design:


The same current mirror was then changed into two rows to achieve a different aspect ratio:



Differential Pair
The layout generator GUI for a differential pair was used to create a Common Centroid layout, and there are over a dozen parameters that you get to control based on your unique objectives:



The antenna effect is mitigated by choosing the option Add Protection Diodes.

STI Effects
Stress effects like Shallow Trench Isolation cause mismatch in transistors as show below where the center MOS device has 25% more stress than the outer devices:



Clicking a checkbox for STI Matching then produces a layout that mitigates stress effects:

Comparison versus Competitors
Cadence has the most mature layout automation technology around called Pcells using SKILL code. Most foundries support the Cadence PDK.

Competitors to Cadence have allied around the concept of Interoperable Process Development Kits (iPDKs). Tanner EDA has joined this alliance and is gradually migrating their tools to support iPDK.

Synopsys offers a tool called Galaxy Custom Designer to automate layout generation.

Mentor Graphics provides the Pyxis Layout Suite to support layout generators.

Ciranova supports analog layout automation with the Helix tools using PyCells based on the Python language.

Magma has a set of Titan FlexCell Libraries.

SpringSoft has created Magic Cell (MCell) for parameterized device generation.

Analog Rails is a smaller company with tools for automating analog layout.

Summary
Accelerating analog layout for IC designers has become much quicker and easy to use with HiPer DevGen from Tanner EDA. These EDA tools have a lower price tag than what you'll find at the public EDA companies and I've found the company very responsive to answering my questions. Here's the HiPer DevGen webinar video, White Paper at EE Times, and a PowerPoint presentation from DAC 2010.

There are plenty of competitors out there offering analog layout automation tools, so you'll have to evaluate which one is the best fit based on: how much control you want, the time to learn, legacy designs, technology node, fab recommendations, experience, and your budget.


[post_title] => A Review of an Analog Layout Tool called HiPer DevGen [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => a-review-of-an-analog-layout-tool-called-hiper-devgen [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:54:09 [post_modified_gmt] => 2019-06-15 01:54:09 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/a-review-of-an-analog-layout-tool-called-hiper-devgen.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [3] => WP_Post Object ( [ID] => 882 [post_author] => 28 [post_date] => 2011-11-27 19:00:00 [post_date_gmt] => 2011-11-27 19:00:00 [post_content] => Some call it co-opetition (collaborative competition), some call it keeping your enemies close. Others call it for what it is, unfair competition and/or other types of legally actionable behavior. GlobalFoundries calls it“Fab Syncing”, which in reality will SINK their FABS!

“With this new collaboration, we are making one of the industry’s strongest manufacturing partnerships even stronger, while giving customers another platform to drive innovation in mobile technology. Customers using this new offering will gain accelerated time to volume production and assurance of supply, and they will be able to leverage significant learning from the foundry industry’s first high-volume ramp of HKMG technology at 32nm in H1 2011,” said Jim Kupec, senior vice president of worldwide sales and marketing at Globalfoundries.

Unfortunately Jim Kupec no longer works for GlobalFoundries and Samsung may be one of the reasons why. In 2010 Globalfoundries and Samsung Electronics said they would synchronize global semiconductor fabrication facilities to produce chips based on a gate-first implementation of 28nm HKMG technology. They will do the same at 20nm switching to Gate-last HKMG. As a result, Globalfoundries and Samsung will be able to make 28nm and 20nm chips for the SAME customers?!?!?!? Putting aside the gritty technical details, what this means is that GFI will have to compete not only with superpower TSMC, but also their PARTNER Samsung. Samsung is not only the second largest semiconductor company, Samsung is also one of the most fiercely competitive companies in the world. Is that really a good idea?

As it turns out it was a very bad idea for a number of reasons. First and foremost is yield. Samsung is the only "Fab Syncing" partner yielding at 28nm Gate-First HKMG (IBM and GFI are not). Remember Samsung is the largest memory maker so they know how to ramp yield quickly at any node. Are they sharing that manufacturing expertise with GFI and other Common Platform members? Not now, not ever. Samsung is aggressively targeting TSMC and GFI 28nm top customers including AMD, Nvidia, Qualcomm, Broadcom, Marvell, and Xilinx.

Cost and delivery are the key components of a wafer manufacturing contract and Samsung is an expert in both areas. Especially since margins for the Samsung foundry business are not broken out so they could literally dump wafers to get market share. TSMC on the other hand has the biggest wafer margins in the industry which they could cut in half and still make money.

The Samsung cut throat culture is inside the company as well. Multiple Samsung groups compete for a given market. Samsung has phones and tablets based on Nvidia, Qualcomm, and TI processors as well as having their own ARM based processors. They compete in the same way with their largest customer Apple. Apple will purchase close to eightBILLION dollars in parts from Samsung for the iSeries of products this year alone, making Apple Samsung’s largest customer. Samsung is also Apple’s largest competitor and now they are engaged in a mega legal battle which will literally change the face of consumer electronics, believe it.

Even the marketing guys are mixing it up with Samsung firing the first shot:



I’m looking forward to Apple’s response and the Samsung response to that etc…

Let’s not forget the Samsung corruption scandalthat engulfed the government of South Korea. Let’s not forget the chip dumping probes. The book "Think Samsung" by ex-Samsung legal counsel accuses Samsung of being the most corrupt company in Asia.

This battle will be bloody entertaining to say the least! Not so much for GFI though, or the other second source foundries as they see already thinning margins get thinner. For us consumers however it means two things: Semiconductor manufacturing innovation and CHEAP CHIPS! w00t!




 [post_title] => GlobalFoundries Versus Samsung! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => globalfoundries-versus-samsung [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:41:34 [post_modified_gmt] => 2019-06-15 02:41:34 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/globalfoundries-versus-samsung.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 883 [post_author] => 20367 [post_date] => 2011-11-27 19:00:00 [post_date_gmt] => 2011-11-27 19:00:00 [post_content] => During the weekend, I read two articles that highlighted Apple’s LCD supply chain build out and started to think of how this would look if Apple were to do the same on the x86 side of the ledger. The two articles, one related to Hitachi and Sony building a new 4” LCD for iphones and a more extensive one on Sharp building a new LCD for the iPAD3 due in 2012 highlight the extent to Apple’s involvement in design and investment to guarantee supply at a much reduced cost so that competitors are left gasping. Turning to the processor world, we know Apple has selected TSMC to Fab their 28nm A6 processor. Why not pull AMD into the Apple-TSMC supply chain ecosystem in order to outmaneuver the raft of Intel based Ultrabook PCs that are headed to the market in 2012?

I will make an assumption that every dollar that Apple invests in Toshiba for NAND Flash capacity and in Sharp for LCDs offers a return that is greater than what they receive for selling iPhones. iPhones are a 60-70% gross margin device, so Apple gains at least $3 for every $1 invested. In addition, it reduces the stature of Samsung as a supplier who now has to compete against the Apple industrial complex. Companies like Sharp have to lay out risk capital to build their plants not knowing if they will be completely filled. As a result they charge higher ASPs to make up for uncertainty and downturns. If they were Walmart or McDonald’s, their cost of capital would be low single digits today. Apple’s investment effectively eliminates the cost of capital risk and put them on a similar plain as Walmart.

AMD’s decision to move to TSMC is difficult in the short term but may allow them to line up their sales with Apple. What AMD needs is a big brother to pick them up on the other side of the Fab switch. Intel’s focus on Ultrabooks was based on Apple’s success with the SSD based MAC Air that was thinner, lighter and longer in battery life than typical notebooks. But these mobiles need a processor with <7W TDP (Thermal Design Point). Apple has noticed that Intel is the only supplier that can keep them from going to 70% market share in the consumer PC space. AMD could help them get around this by building a processor more to Apple’s requirements and at a much lower cost if built in the Apple-TSMC supply chain.

A week ago there was another article speculating that Apple considered using AMD in the current generation of MAC Air, but passed when they thought AMD wasn’t ready on the production side. If Apple were to, under the cloak of darkness, work with AMD on a 28nm and future 20nm APU then the likelihood is that the result would be a $15 - $30 high volume supply of processors that would enable Apple to take the MAC Air down from $999 today to $699, enabling stronger sales and blocking Intel based Ultrabooks from gaining traction.

Looking out two to three years, Apple will probably be TSMC’s largest customer and if Apple invests in its own capacity, it could eliminate the premiums in the processor business. Or to put it another way, AMD would become a design house of x86 processors for Apple who then manages the supply chain.

Apple would still build higher end MAC Air and MAC Book Pro notebooks with Intel processors as it makes its drive into the corporate world the next several years. Corporations are different than consumers in that they work off of a 3-5 year depreciation cycle and therefore the extra dollars spent on a higher end Intel based PC is a better return on investment in the long run. Expect Intel and nVidia to remain in mid range and high end Apple PCs, but for the consumer markets Apple has a chance to lock up huge volumes if they can replace the pricey Intel ULV processors with an AMD version built at TSMC.

AMD has the talent to build great processors, however, we are in an era where the manufacturing costs for processors, NAND flash and LCDs can only be shouldered by companies with lots of cash. Today that means Intel, Samsung and Apple. Apple needs an x86 source to completely wall out competitors in the PC space just as they did with their ARM based CPUs in the iPAD, iPOD and iPhones.

Finally, if Apple successfully pulls AMD into their manufacturing ecosystem, then it will be possible for them to have the upper hand when it comes time to negotiate with Intel on 14nm access for future ARM processors.

FULL DISCLOSURE: I am long AAPL and INTC




 [post_title] => Did Apple Influence AMD’s TSMC Foundry Switch? [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => did-apple-influence-amds-tsmc-foundry-switch [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:41:32 [post_modified_gmt] => 2019-06-15 02:41:32 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/did-apple-influence-amds-tsmc-foundry-switch.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [5] => WP_Post Object ( [ID] => 685 [post_author] => 3 [post_date] => 2011-11-24 09:57:00 [post_date_gmt] => 2011-11-24 09:57:00 [post_content] => I've blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is Better than Cure: DRC/DFM Inside of P&R
Getting to the 32nm/28nm Common Platform node with Mentor IC Tools

If you want some hands-on time with the Calibre tools then consider attending the December 1st workshop in Fremont, California.

[post_title] => December 1st - Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California) [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => december-1st-hands-on-workshop-with-calibre-drc-lvs-dfm-xrc-erc-fremont-california [to_ping] => [pinged] => [post_modified] => 2011-11-24 09:57:00 [post_modified_gmt] => 2011-11-24 09:57:00 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/december-1st-hands-on-workshop-with-calibre-drc-lvs-dfm-xrc-erc-fremont-california.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [6] => WP_Post Object ( [ID] => 879 [post_author] => 20367 [post_date] => 2011-11-24 06:00:00 [post_date_gmt] => 2011-11-24 06:00:00 [post_content] =>  When AMD announced its cutbacks recently many people were left wondering why they were so deep given the strong financial performance in Q3 and the guidance for an up Q4. It couldn’t have been related to the Thailand floods that could have been at most a one-quarter squeeze expected in Q1. Now it is apparent from reports that AMD’s cutbacks were based on the cancelling of its 28nm APUs at Global Foundries and the time required to move to TSMC. The change will significantly delay new APU (CPU+graphics) offerings to address the low cost and “ultrabook” markets. Many companies, especially startups, choose a path that leads to Crossing a Chasm in order to be successful. Since Dirk Meyer’s exit at the beginning of the year, market forces and trends for 2012 are requiring that AMD enter a startup mentality mode and thus have to Cross a Chasm not of its own volition.

Reports earlier this week have Apple on track to be the largest PC supplier in 2012, overtaking HP. The report is based on including the iPAD tablet in the tally, which is proper. The growth of Apple is coming at the expense of all PC players in the $500+ consumer markets in the US and Europe. As a result a re-orientation of market focus has been taking place inside of Intel, nVidia and AMD. Intel has ridden Apple’s MAC coattails and that of the Windows 7 refresh in corporate, but no iPADs. NVidia, surprisingly has also done well in corporate as an attachment to Intel’s Sandy Bridge since Intel’s own graphics were viewed as under par. This left AMD with a main market focus that was the <$500 consumer PCs, especially those in the emerging markets.

AMD’s revenue growth in Q3 and projected growth in Q4 were based on the fact that Intel hit a capacity crunch on its 32nm for most of this year (a fact I noted back in July and which Jen Hsun Huang alluded to in nVidia’s last earnings call). Intel still can’t build enough high-end server processors as gray market prices remain elevated. This means they have to reallocate 32nm wafers away from low-end processors to the server brethren in order to catch up with the shortfall. AMD has thus benefitted with a nice price umbrella. Now that Intel is ramping 22nm Ivy Bridge starting this quarter, we should see PC players begin to launch new mobiles after the Chinese New Year – in the March timeframe. When 22nm starts to ramp, it is likely that 32nm capacity will open up for Intel to go back and supply more product to the emerging markets and remove the price umbrella that AMD enjoys.

The timing of AMD’s 28nm product delay is very serious as there are two underlying trends in the PC market that are dramatically reshaping the industry. The first one that is extremely beneficial to continued growth is the dramatic drop in component prices, especially LCDs that are approaching FREE$ and DRAM that can’t get much lower as a percentage of the overall BOM. The second one is the rise of the Ultrabook, which was enabled by higher density, lower cost, and much smaller footprint NAND Flash storage as a replacement to the traditional 2.5” HDD. The lower cost LCDs means more 14 and 15” notebooks selling for less than $500 and going lower (The true reason Netbooks have died). The NAND trend, means Ultrabooks like MAC Air are the second growth category, but one that can only be addressed by Intel now that AMD has delayed its 28nm APUs. The much thinner Ultrabooks require a much lower processor Thermal Design Power (TDP) of less than 7W to get maximum performance (today Intel is at 17W which means more extensive cooling and CPU throttling). Intel loves this market because they get to increase ASPs by selling the CPU plus the graphics. They also receive a premium for lower power. Expect Ivy Bridge to be delivered with a much lower TDP. As TDP gets lower and lower, the height of the Walled Garden grows, preventing a new competitive entry. Nvidia’s “Project Denver” with Windows 8 is directed at this segment.

As a Company, AMD has to hide out in the emerging consumer market until they fix their 28nm APU product line, but they don’t have long as the NAND trend will eventually make its way into the consumer markets. Today the cheapest NAND based mobile, like the MAC Air is up near $1000 but if you think ahead a couple more generations, then it is possible to see that NAND based Ultrabooks are headed to < $500. AMD needs to be there with ultra low power APU’s to meet the NAND SSD as it overthrows the long reigning 2.5” HDD. And as a final aside, they need to figure out how to get to a much lower TDP, with a smaller, more economical, right- sized die.




 [post_title] => AMD’s Crossing of the Chasm [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => amds-crossing-of-the-chasm [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:41:31 [post_modified_gmt] => 2019-06-15 02:41:31 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/amds-crossing-of-the-chasm.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [7] => WP_Post Object ( [ID] => 864 [post_author] => 28 [post_date] => 2011-11-23 19:00:00 [post_date_gmt] => 2011-11-23 19:00:00 [post_content] => Interesting story, for my wife’s 50th birthday we went to Las Vegas to see Sir Elton John in concert. My wife is an Elton fan and this may be her last chance to see him live so off we went. I saw Elton and Billy Joel in a dueling piano concert a while back and it was simply amazing! The underlying purpose of the trip however was to earn “Perfect Husband Points” (PHP’s), which can then be traded in for sailing trips in Mexico etc… Right now I’m saving up for a trip to Spain to run with the bulls.

When we checked in ( Caesar’s Palace Las Vegas ) the desk lady asked us which part of the hotel we would like to stay in. We could be near the registration desk for convenience, or we could be near the topless pool, or be near the chapels. Without hesitation, I said near the chapels please (+1,000 PHP’s). Okay, I may have hesitated briefly, but come on, who knew there would be a topless pool!

After getting settled in our suite (500+ PHP’s) we took a walk around the hotel and stopped by the chapels to see what a wedding at Caesar's is all about. There were three chapels one large, one medium, and one small, all very beautiful! The wedding coordinator told us that a marriage renewal costs $350.00 and included a quick service in the small chapel and a decorative certificate. So I got down on one knee and asked my wife to marry me again (+5000 PHPs) and luckily she said yes.

The wedding coordinator then told us that a deluxe wedding had just cancelled and if we could be ready at 6pm (1+ hour) we could have it for the $350.00 price we already agreed to! Such a deal! The large chapel, flowers, champagne, pictures, all inclusive, how could we pass that up! (+1000 PHP’s)

Strangely enough we were both nervous even after being together for 30+ years. Even stranger, she did not cry at our first wedding but she cried tears of joy at this one as the picture shows. I didn’t cry, probably because I was more focused on the honeymoon part. We even bought a new ring for me which I have not taken off since (+2000 PHP’s).

The Elton John “Million Dollar Piano” concert was outstanding, he is still quite the showman. His piano probably cost a million dollars, thus the name. The piano was four years in the making, is covered with 68 LED screens, and weighs 3,200 pounds! The piano lit up with color and imagery to reflect the theme of each song, it was amazing! Such technology! Brought to you by the semiconductor design and manufacturing ecosystem!

The other technology that was glaring in our faces were the smartphones that people held up to take pictures and video of the event. Of course we were constantly reminded that photos and video were NOT allowed but the majority of people did it anyway. Another example of smartphone inspired anarchy!


[post_title] => What happens in Las Vegas Gets Blogged on SemiWiki! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => what-happens-in-las-vegas-gets-blogged-on-semiwiki [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:41:30 [post_modified_gmt] => 2019-06-15 02:41:30 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/what-happens-in-las-vegas-gets-blogged-on-semiwiki.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [8] => WP_Post Object ( [ID] => 878 [post_author] => 4 [post_date] => 2011-11-23 05:21:00 [post_date_gmt] => 2011-11-23 05:21:00 [post_content] => Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. Sgroi et al. call "the layered-stack approach to the design of the on-chip intercore communications the Network-on-Chip (NOC) methodology." In a NoC system, modules such as processor cores, memories and specialized IP blocks exchange data using a network as a "public transportation" sub-system for the information traffic. A NoC is constructed from multiple point-to-point data links interconnected by switches (a.k.a. routers), such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches. A NoC is similar to a modern telecommunications network, using digital bit-packet switching over multiplexed links. Although packet-switching is sometimes claimed as necessity for a NoC, there are several NoC proposals utilizing circuit-switching techniques. This definition based on routers is usually interpreted so that a single shared bus, a single crossbar switch or a point-to-point network are not NoCs but practically all other topologies are. This is somewhat confusing since all above mentioned are networks (they enable communication between two or more devices) but they are not considered as network-on-chips. Note that some articles erroneously use NoC as a synonym for mesh topology although NoC paradigm does not dictate the topology. Likewise, the regularity of topology is sometimes considered as a requirement which is, obviously, not the case in research concentrating on "application-specific NoC topology synthesis".


An interesting white paper from Arteris: “Routing Congestion: The Growing Cost of Wires in Systems-on-Chip” demonstrates how you can drastically reduce routing congestion by using a NoC. On this picture, you can see on the left part, the routing congestion areas, highlighted through a color code (purple= very strong congestion, red=strong congestion, yellow=medium, blue=no congestion), this will sounds familiar to anybody who has already used a floor planning tool. According with Jonah Probell: “…in the process of chip design, more can be done to improve P&R wire congestion by reducing the number of wires in the IP RTL before synthesis.”




For those like me who have used floor planning tools in the mid 90’s, to help customers to release to layout the RTL version of a chip with good chance to complete the lay out phase within a decent time period (say, a couple of weeks, as these chips were designed into a supercomputer, using the largest available BiCMOS base array, running at the highest possible internal frequency, which makes sense when you design a supercomputer…), it was common to spend weeks if not MONTHS to optimize the floor plan of the IC. I realize now that having the opportunity to use a NoC at that time would certainly help us to, either reduce the design cycle (thus the Time To Market for our customer, as well as the time spent by TI FAE team), either go higher in frequency, and help our customer to launch a more powerful product. I strongly encourage anybody involved (or interested) by on the edge SoC design techniques to download this paper from Arteris here.


Eric Esteve from IPNEST




[post_title] => How to use NoC to avoid routing congestion [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => how-to-use-noc-to-avoid-routing-congestion [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:41:27 [post_modified_gmt] => 2019-06-15 02:41:27 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/how-to-use-noc-to-avoid-routing-congestion.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [9] => WP_Post Object ( [ID] => 877 [post_author] => 4057 [post_date] => 2011-11-22 19:59:00 [post_date_gmt] => 2011-11-22 19:59:00 [post_content] => Flash analog-to-digital converters (ADCs) are commonly used in high-frequency applications such as satellite communications, sampling oscilloscopes, and radar detection. Flash ADC is preferred over other ADC architectures because it is extremely fast and quite simple. However, flash ADC typically requires twice as many converters per bit for higher accuracy requirements, which increases the size of the chip (and likewise the cost).

Not surprisingly, at small process nodes, the influence of parasitic elements on these sensitive mixed-signal designs is growing, due to the increasing interactions between devices and interconnects that are in close proximity. Circuits are highly sensitive to these parasitic effects, so accurate parasitic extraction is critical for first silicon success.

Constraints used to lay out a flash ADC are also extremely important, because differential pairs must have symmetrical layouts, identical capacitors must have equal values, and resistors must be matched. For example, if one resistor must be over-etched because of process variation sensitivity, all of the resistors must be over-etched in the same way to ensure that the taps off the resistor ladder are still the correct voltage value. Several guidelines can help improve layout matching.

Designing flash ADCs requires careful tradeoffs between speed, accuracy, and power. Highly accurate parasitic extraction ensures that parasitics will not cause the ADC to behave incorrectly, and that the ADC will still meet all of the design specifications.

New 3D parasitic extraction technology applied to a flash ADC circuit design reduces the need for extra guardbanding, while ensuring the circuitry will work according to the specifications when manufactured.

You can download the complete "Reducing the Need for Guardbanding a Flash ADC Design" whitepaper HERE.

About the Author:
Karen Chow is the Technical Marketing Engineer for Calibre xRC and Calibre xACT 3D at Mentor Graphics in Wilsonville, OR. She has worked on both sides of the EDA industry, designing analog ICs and supporting EDA tool development. Karen has her BSc in electrical engineering from the University of Calgary, and her MBA from Marylhurst University. In her spare time, she enjoys playing music in bands, designing clothing and handbags, and quilting.







var _gaq = _gaq || [];
_gaq.push(['_setAccount', 'UA-26895602-2']);
_gaq.push(['_trackPageview']);

(function() {
var ga = document.createElement('script'); ga.type = 'text/javascript'; ga.async = true;
ga.src = ('https:' == document.location.protocol ? 'https://ssl' : 'http://www') + '.google-analytics.com/ga.js';
var s = document.getElementsByTagName('script')[0]; s.parentNode.insertBefore(ga, s);
})();


 [post_title] => Reducing the Need for Guardbanding Flash ADC Designs [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => reducing-the-need-for-guardbanding-flash-adc-designs [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:54:03 [post_modified_gmt] => 2019-06-15 01:54:03 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/reducing-the-need-for-guardbanding-flash-adc-designs.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 886 [post_author] => 9491 [post_date] => 2011-11-29 08:00:00 [post_date_gmt] => 2011-11-29 08:00:00 [post_content] =>  One of the challenges with today's SoCs is that chip-finishing, putting the final touches to the SoC working at the chip level, stresses layout editors to the limit. Either they run out of capacity to load the entire chip, or they can handle the entire chip but everything is like wading through molasses, it takes an awfully long time to get anything done.

As a result there are a number of chip viewer tools that focus just on being able to load the SoC and very fast to display. The problem with these is that editing capabilities are either non-existent, it is strictly a viewer, or extremely limited.

 Laker's Blitz is a tool that brings the best of both worlds. It can handle extremely large designs and is between 5 and 20 times faster than regular layout editors. However, it has most of the editing features that regular layout editors have since it is built on top of Laker Custom Layout. It has the same user-interface, same basic editing, same in-memory schema, same integration with DRC/LVS, and the same Tcl extensions.

Blitz is optimized for chip-level operations on very large chips, basically reading GDS, editing, and then writing the GDS back out again. The four big tasks it has been optimized for are:

  • Chip-finishing: chip-level review, editing, assembly and debugging
  • IP merging: replacing IP black-boxes with physical layout
  • SoC assembly and review: assemble IP blocks, trace critical nets, verify and fix boundary DRC errors
  • DRC review and repair: chip-level signoff DRC

Of course not every single thing that you can do in Laker Custom Layout is supported, otherwise it would make no sense to have two tools. In particular, Laker Blitz is 64-bit only, it cannot create or modify Pcells and so on. It is focused strictly on the typical tasks done at the chip level with today's advanced technology node SoCs.




 [post_title] => Blitz, blazing fast layout [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => blitz-blazing-fast-layout [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:41:35 [post_modified_gmt] => 2019-06-15 02:41:35 [post_content_filtered] => [post_parent] => 0 [guid] => https://35.226.139.164/uncategorized/886-blitz-blazing-fast-layout/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 1 [filter] => raw ) [comment_count] => 0 [current_comment] => -1 [found_posts] => 7103 [max_num_pages] => 711 [max_num_comment_pages] => 0 [is_single] => [is_preview] => [is_page] => [is_archive] => [is_date] => [is_year] => [is_month] => [is_day] => [is_time] => [is_author] => [is_category] => [is_tag] => [is_tax] => [is_search] => [is_feed] => [is_comment_feed] => [is_trackback] => [is_home] => 1 [is_privacy_policy] => [is_404] => [is_embed] => [is_paged] => 1 [is_admin] => [is_attachment] => [is_singular] => [is_robots] => [is_favicon] => [is_posts_page] => [is_post_type_archive] => [query_vars_hash:WP_Query:private] => 2f0ca05703ff803502df0522c0379dab [query_vars_changed:WP_Query:private] => [thumbnails_cached] => [stopwords:WP_Query:private] => [compat_fields:WP_Query:private] => Array ( [0] => query_vars_hash [1] => query_vars_changed ) [compat_methods:WP_Query:private] => Array ( [0] => init_query_flags [1] => parse_tax_query ) [tribe_is_event] => [tribe_is_multi_posttype] => [tribe_is_event_category] => [tribe_is_event_venue] => [tribe_is_event_organizer] => [tribe_is_event_query] => [tribe_is_past] => [tribe_controller] => Tribe\Events\Views\V2\Query\Event_Query_Controller Object ( [filtering_query:protected] => WP_Query Object *RECURSION* ) )

Blitz, blazing fast layout

Blitz, blazing fast layout
by Paul McLellan on 11-29-2011 at 8:00 am

One of the challenges with today’s SoCs is that chip-finishing, putting the final touches to the SoC working at the chip level, stresses layout editors to the limit. Either they run out of capacity to load the entire chip, or they can handle the entire chip but everything is like wading through molasses, it takes an awfully … Read More


Will Amazon’s Kindle Fire Force x86 Processors To Revisit the 1980s?

Will Amazon’s Kindle Fire Force x86 Processors To Revisit the 1980s?
by Ed McKernan on 11-29-2011 at 12:07 am

What if Amazon’s new Kindle Fire, priced at $199 and using a sub $10 TI processor, has effectively started the ball rolling towards forcing Intel and AMD to building a Very Low Cost (perhaps even <$10) x86 mobile processor? A recent article entitled “Amazon’s Risky Strategy” explores the ramifications of Amazon selling Kindle… Read More


A Review of an Analog Layout Tool called HiPer DevGen

A Review of an Analog Layout Tool called HiPer DevGen
by Daniel Payne on 11-28-2011 at 1:11 pm

My last IC design at Intel was a Graphics Chip and I developed a layout generator for Programmable Logic Arrays (PLA) that automated the task, so I’ve always been interested in how to make IC layout more push-button and less polygon pushing. Today I watched a video about HiPer DevGen from Tanner EDA and wanted to share what I … Read More


GlobalFoundries Versus Samsung!

GlobalFoundries Versus Samsung!
by Daniel Nenni on 11-27-2011 at 7:00 pm

Some call it co-opetition (collaborative competition), some call it keeping your enemies close. Others call it for what it is, unfair competition and/or other types of legally actionable behavior. GlobalFoundries calls it“Fab Syncing”, which in reality will SINK their FABS!

“With this new collaboration, we are making one Read More


Did Apple Influence AMD’s TSMC Foundry Switch?

Did Apple Influence AMD’s TSMC Foundry Switch?
by Ed McKernan on 11-27-2011 at 7:00 pm

During the weekend, I read two articles that highlighted Apple’s LCD supply chain build out and started to think of how this would look if Apple were to do the same on the x86 side of the ledger. The two articles, one related to Hitachi and Sony building a new 4” LCD for iphones and a more extensive one on Sharp building a new LCD for the iPAD3… Read More


December 1st – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)

December 1st – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)
by Daniel Payne on 11-24-2011 at 9:57 am

I’ve blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is BetterRead More


AMD’s Crossing of the Chasm

AMD’s Crossing of the Chasm
by Ed McKernan on 11-24-2011 at 6:00 am

When AMD announced its cutbacks recently many people were left wondering why they were so deep given the strong financial performance in Q3 and the guidance for an up Q4. It couldn’t have been related to the Thailand floods that could have been at most a one-quarter squeeze expected in Q1. Now it is apparent from reports that AMD’s … Read More


What happens in Las Vegas Gets Blogged on SemiWiki!

What happens in Las Vegas Gets Blogged on SemiWiki!
by Daniel Nenni on 11-23-2011 at 7:00 pm

Interesting story, for my wife’s 50th birthday we went to Las Vegas to see Sir Elton John in concert. My wife is an Elton fan and this may be her last chance to see him live so off we went. I saw Elton and Billy Joel in a dueling piano concert a while back and it was simply amazing! The underlying purpose of the trip however was to earn “Perfect… Read More


How to use NoC to avoid routing congestion

How to use NoC to avoid routing congestion
by Eric Esteve on 11-23-2011 at 5:21 am

Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. Sgroi et al. call “the layered-stack approach to the design of the on-chip intercore communications the Network-on-Chip (NOC) methodology.” In a NoC system, modules such as processorRead More


Reducing the Need for Guardbanding Flash ADC Designs

Reducing the Need for Guardbanding Flash ADC Designs
by SStalnaker on 11-22-2011 at 7:59 pm

Flash analog-to-digital converters (ADCs) are commonly used in high-frequency applications such as satellite communications, sampling oscilloscopes, and radar detection. Flash ADC is preferred over other ADC architectures because it is extremely fast and quite simple. However, flash ADC typically requires twice as many… Read More