A couple of days ago Intel announced a collaboration with eASIC. Here is the opening paragraph of the press release:Intel Corporation today announced plans to develop integrated products with eASIC Corporation that combine processing performance and customizable hardware to meet the increasing demand for custom compute solutions for data centers and the “cloud.” The new parts will enable acceleration of up to two times that of a field programmable gate array (FPGA) for workloads like security and big data analytics while also speeding the time to market for custom application specific integrated circuit (ASIC) development by as much as 50 percent.
Nowhere in the press release does it say whether or not Intel will be manufacturing parts for eASIC nor whether the intention is to integrate the eASIC technology onto the same die as the microprocessor. My guess would be that the plan is to use some sort of package-in-package technology but that they will be separate die. In the past eASIC has used Fujitsu and GlobalFoundries for manufacture and the most advanced arrays they have are at 28nm.
The first conclusion that everyone has leapt to is that this Intel’s reaction to its failure to acquire Altera recently. I don’t think that this is true.
eASIC’s boilerplate in the press release reads:eASIC is a semiconductor company offering a differentiated solution that enables us to rapidly and cost-effectively deliver custom integrated circuits (ICs), creating value for our customers’ hardware and software systems. Our eASIC solution consists of our eASIC platform which incorporates a versatile, pre-defined and reusable base array and customizable single-mask layer, our easicopy ASICs, our standard ASICs and our proprietary design tools.
If I interpret this correctly then the array is programmed with a single metal layer. Clearly it is possible to build accelerators for datacenter applications using this technology but they are not reprogrammable once they have been manufactured. It seems to me that what is required for datacenter accelerators is the capability to dynamically reconfigure the accelerator to do whatever is required, visual search at one moment, then voice recognition the next moment. FPGAs such as those from Xilinx and Altera can do this. I don’t know in detail about Altera’s capabilities but I do know that Xilinx can even reconfigure part of an array while keeping the rest of the array running an application during the reprogramming. So part of the array could be doing voice-recognition, say, while another part of the array is being set up for facial recognition. Even if Altera is not that flexible, they can still reprogram the entire array depending on what acceleration is required. These algorithms are by no means stable and so the capability to fix bugs and to upgrade the hardware performance as the algorithms improve seems like something important.
On the other hand, Intel also says:This collaboration is part of Intel’s strategy to integrate reprogrammable technology with Intel Xeon processors to greatly improve performance, power and cost.
But it seems a bit of a stretch to call eASIC’s technology reprogrammable unless I have completely misunderstood things. It is programmable at manufacture, and the bases can be banked to keep turnaround time low. It has an FPGA-like flow making for fast design and better power and performance than a true FPGA, but it seems to lack the most important feature: true reprogrammability.
Obviously this is some sort of a shot across ARM’s bows since they and their partners (such as Cavium, Qualcomm and more) are trying to infiltrate the datacenter with lower cost, lower power and lower physical form factor (and lower performance but not by much). Xilinx’s Zynq arrays contain multicore ARM processors as well as a lot of programmable fabric and might be ideally suited to some of these types of applications that require more acceleration than can be obtained from just a processor, not matter how fast.Share this post via: