PCIe Webinar Banner
WP_Term Object
    [term_id] => 50
    [name] => Events
    [slug] => events
    [term_group] => 0
    [term_taxonomy_id] => 50
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 1257
    [filter] => raw
    [cat_ID] => 50
    [category_count] => 1257
    [category_description] => 
    [cat_name] => Events
    [category_nicename] => events
    [category_parent] => 0

"An art can only be learned in the workshop of those who are winning their bread by it"

"An art can only be learned in the workshop of those who are winning their bread by it"
by Paul McLellan on 05-13-2015 at 7:00 am

 That was said by the novelist Samuel Butler, but it is not a bad description of why you should spend the Sunday at DAC in one of the workshops that are taking place that day.

One workshop is on Design Automation for Beyond CMOS Technologies. Before getting to design automation, it is good to start with which technologies are potentially on deck for after CMOS. I spoke with Rasit Topaloglu who is one of the organizers of the workshop. He is in development in the IBM Systems Group working on next generation computer systems. To give some focus to the workshop they decided to focus on what technologies might be used for high-performance computing (HPC) once we get beyond CMOS and even beyond charge-based computing (so carbon nanotube counts as CMOS in this definition!).

The workshop opens with a keynote from Philip Wong of Stanford titled Memory Leads the Way to Better Computing: the N3XT 1000X in Energy Efficiency.

There are then 3 sessions, each with 3 papers and a panel session at the end. There is a mixture of people from academia and industry (on the industry side there are presentations from Intel, GlobalFoundries and imec). The first session is on Architecture and how emerging devices will change architecture perhaps beyond the traditional von Neumann model. After lunch, there is a session on Spin Logic. The fact that this is the session where both imec and Intel are presenting shows how serious the investment in the area is. The final session is on New Materials, Design and Modeling, which is just what it says on the label. One presentation on new materials (topological insulators), one on design (from GF) and one on modeling.

There are 8 more workshops in addition to the “to infinity and beyond” one.


  • Low Power Image Recognition Challenge. This workshop is a programming contest. Registration is available for attendees to observe the participants. There is no workshop presentation.
  • See above.
  • SEAK 2015: DAC Workshop on Suite of Embedded Applications and Kernels. This workshop is a venue for the DARPA SEAK project to interact with the broader embedded community.
  • System to Silicon Performance Modeling and Analysis. The integration of heterogeneous electronic systems composed of SW and HW requires not only a proper handling of system functionality, but also an appropriate expression and analysis of various extra-functional properties: timing, energy consumption, thermal behavior, reliability, cost and others as well as performance aspects related to caching, non-determinism, probabilistic effects.
  • Computing in Heterogeneous, Autonomous ‘n’ Goal-Oriented Environments. As the push for parallelism continues to increase the number of cores on a chip, system design has become incredibly complex; optimizing for performance and power efficiency is now nearly impossible for the application programmer.
  • Design Automation for HPC, Clouds and Server-class SoCs. Traditionally SoC design methods have focused on low-power consumer electronics or high performance embedded applications. But now SoC design methods are moving into high-end computing due to the emergence of embedded IP offering capable double-precision floating point, 64-bit address capability, and options for high performance I/O and memory interfaces. System on Chip (SoC) integration is able to further reduce power, increase integration density, and improve reliability.
  • Requirements-driven Verification (for Standards Compliance). Requirements-driven verification is based on ensuring that feature-level requirements are adequately verified by tracing such requirements through to verification tasks.
  • Enterprise-level IP Management for the DAC Semiconductor Professional. This workshop addresses a burgeoning problem for semiconductor companies – managing the vast amount of IP that is being produced and consumed by their design teams. Over the last 20 years, we have seen the transition from almost no IP reuse to some modern SoC’s owing nearly 90% of their functionality to reused or purchased IP.
  • Interdisciplinary Academia-industry Collaboration Models and Partnerships. Design Automation as well as circuit design and implementation did NOT get easier recently! Even in challenging economic situations industry has to find ways to partner closely with academia to ensure continued leading edge research and education.

    Most of these workshops run from around 9am to around 4.30pm. Check the DAC website for up-to-date times and the rooms where the workshops will be held. Then at 5.30 you can walk over to the Intercontinental Hotel in time for the traditional Sunday night DAC reception.

    The DAC workshop page is here.

    Share this post via:

  • Comments

    There are no comments yet.

    You must register or log in to view/post comments.