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Early Structural Reliability Analysis of a Chip-Package-System design is a must!

Early Structural Reliability Analysis of a Chip-Package-System design is a must!
by Tom Dillinger on 02-10-2016 at 11:00 am

2015 will be remembered as the year when chip-package-system (CPS) physical co-design and electrical/thermal analysis methodologies took center stage.

The wider adoption of advanced 2.5D/3D packaging and aggressive form factor printed circuit technologies accentuated the difficulties in building electrical models for analyzing high-speed signals and the power distribution network (PDN) — a much greater diversity of interdependent data from disparate design domains needed to be consolidated. These technologies led to an increase in (local) power density and greater power gradients, necessitating building thermal models for analysis, as well.

In an earlier Semiwiki article, an example of a CPS analysis flow for signal integrity (SI), power integrity (PI), and thermal simulation from Ansys was highlighted (link).

In 2016, there will be two emerging trends:

(1) The growing automotive, aerospace, IoT, and server markets will be laser-focused on assessing product reliability during design phase implementation — this analysis can no longer simply be relegated to a final product pre-ship qualification stress test.

(2) The complexity of reliability analysis requires a CPS methodology that “breaks down the walls” between electrical and mechanical model generation. To enable early reliability analysis, structural models need to be available from CPS design data quickly and accurately.

Last year, the EDA product focus for CPS analysis was on providing a collaborative platform for chip designers, package/board layout designers, and SI/PI engineers, enabling efficient electrical data model generation and simulation.

This year, given the two trends mentioned above, the EDA focus will be on a CPS methodology that embraces mechanical analysis, as well. Specifically, a structural analysis of material deformation (X, Y, and Z) and solder connection stresses is required, due to anticipated thermal gradients across chip-to-package and package-to-board.

Leveraging their expertise in mechanical finite-element modeling and simulation, Ansys has recently announced significant enhancements (in R17.0) to their CPS methodology, with an expedited path to building a structural model for analysis with their Multiphysics toolset. I recently had an opportunity to chat with Margaret Schmitt, Director of Business Development at Ansys, to learn about these new features.

Margaret emphasized that this new release was driven by the goal of much greater analysis productivity, through focus on providing “workflow” support within the tool suite, and improved model generation techniques across domains. (To be sure, the HPC parallel/distributed computing throughput and 3D model visualization capabilities remain a product focus, too.)

The figure above highlights the overall Ansys R17.0 flow. The RedHawk tool suite is used to generate Chip Power Model (CPM) and Chip Thermal Model (CTM) abstracts. The SIwave suite — specifically, the DC PDN analysis feature — is used to derive the (package/board) DC current distribution throughout the plane layers. These PDN currents are a significant contribution to resistive power losses and (Joule heating) temperature gradients.

With the SIwave DC results for the PDN and the Chip Thermal Models, a computational fluid dynamics (CFD) analysis is done by Ansys Icepak, to determine the overall thermal profile. Note that the flow arrow between SIwave and Icepak in the methodology figure above is bidirectional — the PDN currents (with the chip CPM abstracts) are strongly temperature dependent, necessitating a brief iterative solution approach to a converged thermal result.

The two figures below illustrate the SIwave-Icepak workflow assistants within the CPS methodology, followed by an example of the SIwave DC heating loss results and the corresponding Icepak thermal profile.

The key enhancement in the R17.0 release focuses on productivity of mechanical model generation for deformation/stress analysis. In addition to the thermal profile results from Icepak, the structural model requires a representation of local metal density on each layer, as this density has a major impact on the mechanical parameters of the composite cross-section. The new Ansys “trace metal mapping and model generation” feature automates this data transfer from the electrical to mechanical domain.

The figure above illustrates how the metal layer data is imported into Multiphysics, plus an example of a Z-deformation and stress calculation.

There are several videos and app notes from Ansys describing the new the new CPS mechanical analysis methodology, which are available here.

Additionally, Ansys will be conducting a webinar highlighting these new R17.0 CPS productivity features on March 1st — to register for this webinar, please use this link.

2016 will indeed be the year for faster and more accurate CPS co-operative analysis across electrical, thermal, and mechanical domains, in support of the reliability analysis required by growing semiconductor markets.



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