EDA Interoperability at DAC

EDA Interoperability at DAC
by Daniel Payne on 06-17-2011 at 4:42 pm

Intro
My Wednesday breakfast at DAC last week was at the Interoperability event sponsored by Synopsys. The Synopsys moderator was so jovial that he reminded me of Jerry Lewis, I was relieved when the guests gave us an update.

Notes
Interconnect Modeling- Open Source Interconnect Technology Format (ITF)o Used by Star RC

–… Read More


One Trillion Transistor IC Layout at DAC

One Trillion Transistor IC Layout at DAC
by Daniel Payne on 06-17-2011 at 4:20 pm

Intro
Micro Magic was the only company at DAC that showed an IC layout editor with 1 Trillion transistors loaded in it, wow.


Karen Mangum

Notes
I chatted with Katherine Hays, a 12 year veteran of Micro Magic about what was new at DAC this year.

Max-3D – Can handle stacked wafers with TSV
– Gary Smith’s list of must-see for 3D
–… Read More


Berkeley Design Automation at DAC

Berkeley Design Automation at DAC
by Daniel Payne on 06-17-2011 at 4:01 pm

Intro
Simon Young, Product Marketing manager at BDA gave me an update at DAC last week on their circuit simulator, Analog Fast SPICE (AFS).

Notes

Quarterly release: 2011 Q2 now

Speed Improvements: Still 5 to 10X speed improvement over other SPICE tools

Multi-Threading – 2 to 4 X improvement using 4 to 8 cores.

Device Noise – three … Read More


GlobalFoundries Production-Ready @ 28nm in Multiple Locations!

GlobalFoundries Production-Ready @ 28nm in Multiple Locations!
by Daniel Nenni on 06-15-2011 at 11:02 am

GLOBALFOUNDRIES showed off its 28nm design ecosystem at #48DAC last week in San Diego. The company featured a full design ecosystem for its 28nm High-k Metal Gate (HKMG) technology, including silicon-validated flows, process design kits (PDKs), design-for-manufacturing (DFM), and intellectual property (IP) in partnership… Read More


Synopsys IC Validator at DAC

Synopsys IC Validator at DAC
by Daniel Payne on 06-14-2011 at 3:14 pm

Intro
At DAC last week I visited the Synopsys demo suite to see what’s new with IC Validator.


Notes
Stelios Diamantidis, PMM
– In-design physical verification
– Sign-off reveals thousands of late stage DRC violations
– 28nm has 1.5K rules, 15K runset sizes
– Metal Fill changes timing
– The… Read More


Extreme DA at DAC

Extreme DA at DAC
by Daniel Payne on 06-14-2011 at 3:01 pm

Intro
Over the lunch hour on Tuesday at DAC I met with Emre Tuncer, VP – Product Engineering & Applications and heard about extraction and timing analysis.

Notes

GoldX – parasitic extractor. Fast extractor, recently announced, all new technology, early customer adoption. One customer deploying it in 40nm, soon to be 28nm.… Read More


Tanner EDA at DAC

Tanner EDA at DAC
by Daniel Payne on 06-14-2011 at 2:40 pm

Intro
For 22 years now Tanner EDAhas been in the business pf offering tools for AMS and MEMS designers. I learned what’s new at DAC on Tuesday morning.

Notes
Nicholas Williams – Director of Product Management

Tanner EDA front end: S-Edit integrates with Berkeley Fast Analog Simulator
W-Edit – is the waveform viewer

Who is … Read More


Blue Pearl at DAC

Blue Pearl at DAC
by Daniel Payne on 06-14-2011 at 1:03 pm

Intro
It’s all about analyzing RTL and creating timing constraints at Blue Pearl, so I stopped by their booth on Tuesday morning to get an update on what’s new for 2011.

Notes

What’s New in 2011 at Blue Pearl Software

New designer experience, ease of use. Brand new GUI.

Work with RTL to synthesis tools to get best timingRead More


Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 2 of 2)

Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 2 of 2)
by Daniel Payne on 06-14-2011 at 12:43 pm

Dipesh Patel, VP Engineering, ARM Physical IP

Consumer demand for smart devices, short life cycles (SmartPhone, Tablets, Internet screens)

Processor speeds: 1GHz to 1.5GHz
SOC Memory: 600MHz to 1.2 GHz
How power efficient?
How is the layout density?

Standard Cells: multi-channel, multi-vt (4) libraries

Memory Compilers:Read More


Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 1 of 2)

Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 1 of 2)
by Daniel Payne on 06-14-2011 at 12:26 pm

Intro
The 28nm nodes is ready with foundry silicon, IP and EDA tools. Tuesday morning at the DAC breakfast I learned more about the 28nm eco-system.

Notes
Why 32/28nm
Lower power, high integration requirements, mobile applications

What is Ready?
IP is qualified (ARM, Memories, Foundation IP, SNPS IP, PDKs)
Read More