DVCon is an annual Design and Verification Conference that started out in Silicon Valley, then expanded by adding India as a new location. Our semiconductor design and verification world is global in stature, so if you’re living in the region then consider registering for this event held Thursday and Friday, September 15-16 at the Leela Palace in Bangalore. Attendees have two technical tracks to choose from: ESL, Design Verification. Yes, everyone is quite busy, but by taking a few days off your regular work schedule you have the possibility of gaining back weeks of time by using new techniques described at DVCon 2016.
Let me give you five good reasons to attend this month.
1. Wally Rhines, CEO, Mentor Graphics
I’ve attended dozens of speeches by Wally over the decades and he has some of the richest infographics around that are packed with facts and figures about the semiconductor history and where it’s headed. He will be the keynote speaker on Thursday from 9:45 AM – 10:30 AM, and will be talking about design verification needs and trends. Learn about functional verification, security and safety.
2. ESL Tutorial
Thinking about using C++ or SystemC in a HLS design and verification flow, or just want to get more efficient? There’s a tutorial on Thursday that should fit your curiosity called, “A Verification Methodology for High-level Synthesis – From C++/SystemC to RTL Signoff“. Sandeep Dager of Mentor Graphics will conduct this tutorial and cover 8 points:
- Basics concepts of HLS
- Overview of a High-level Design and Verification flow
- Introduction of use of formal C property checking to verify the HLS source is clean for synthesis
- Closing on coverage for the HLS source
- Basic synthesis flow to perform design space exploration for area, performance, and power
- Re-Use of high level verification model and test vectors in RTL simulation for closure
- Using existing RTL verification tools and methodologies to close on 100% RTL coverage
- Fundamentals of performing an ECO with HLS
3. Low Power Tutorial
Challenged by using multiple power domains, too many power states and how to keep your power management working properly? The tutorial from Srikanth Nuni and Praveen Shukla of Mentor Graphics will answer these questions in their tutorial, “Advanced Validation and Functional Verification Techniques for Complex Low Power System-on-Chips“. Four major concepts will be covered:
- Using static power-aware checking
- Power-aware simulation with UPF and reaching coverage closure
- Estimating system power consumption under software loads by using emulation
- System-level power modeling with SystemC code
4. UVM Tutorial
Defining a coverage metric and then implementing a verification methodology that is driven by coverage makes sense, but how do you go about doing this well? Pradeep Salla and Keshav Joshi from Mentor Graphics have put together a UVM tutorial called, “An Industry Proven UVM Reuse Methodology for Coverage Driven Block Level Verification to Software Driven Chip Level Verification Across Simulation and Emulation“. You’ll learn approaches like:
- Software and hardware co-simulation
- UVM reuse methodology
- Using a code generator
5. Accellera Tutorial
The Portable Stimulus Standard (PSS) promises a boost in verification productivity by reusing test cases. Going beyond just IP blocks, the upcoming PSS spec aims to help out reuse at the subsystem and full-chip levels. Larry Melling from Accellera will be presenting his tutorial, “How Portable Stimulus Addresses Key Verification, Test Reuse, and Portability Challenges“. Learn about:
- Upcoming changes to the PSS specification
- Testing at the IP level, SoC, emulation, FPGA prototyping and silicon
- Linking verification to diagnostics and software
- Common usage examples
- Portability challenges
There you have it, at least five reasons to register and attend the DVcon 2016 in India later this month. This conference and exhibition will be packed for two days, so start filling up your calendar with the most important tutorials, keynotes and vendor meetings.