The State of FPGA Functional Verification

The State of FPGA Functional Verification
by Daniel Payne on 02-15-2023 at 10:00 am

Design Styles min

Earlier I blogged about IC and ASIC functional verification, so today it’s time to round that out with the state of FPGA functional verification. The Wilson Research Group has been compiling an FPGA report every two years since 2018, so this marks the third time they’ve focused on this design segment. At $5.8 billion… Read More


The State of IC and ASIC Functional Verification

The State of IC and ASIC Functional Verification
by Daniel Payne on 02-09-2023 at 10:00 am

Silicon Spins min

Way back in 2002 there was a study from Collett International Research on functional verification, and since 2010 the Wilson Research Group has continued that same kind of study with a new report every two years. What attracts me to this report is that it doesn’t just look at the installed base of one EDA vendor, instead it looks… Read More


Israel and Automotive Safety. More Active Than You May Think.

Israel and Automotive Safety. More Active Than You May Think.
by Bernard Murphy on 10-21-2020 at 10:00 am

autonomy min

CadenceLIVE ran a session recently in Europe which I thought would be interesting to check out, especially around automotive needs. The live sessions were too early/late for me (middle of the night) and sadly the talks I really wanted to hear weren’t recorded. Instead, I dug around for updates on automotive electronics in Europe.… Read More


Questa Clock/Reset Domain Crossing Verification / Mentor Functional Safety Compliance – What’s New in Functional Verification from Mentor: Session 5

Questa Clock/Reset Domain Crossing Verification / Mentor Functional Safety Compliance – What’s New in Functional Verification from Mentor: Session 5
by Admin on 05-27-2020 at 12:12 am

Register For This Web Seminar

Online – Jun 11, 2020
4:00 PM – 5:00 PM Europe/London

Online – Jun 11, 2020
4:00 PM – 5:00 PM US/Pacific

This is the fifth of a 5-part series on “What’s New in Functional Verification from Mentor.” Each session will be presented twice at the times shown above

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Questa Formal-Based Apps / Questa Formal Property Checking – What’s New in Functional Verification from Mentor: Session 4

Questa Formal-Based Apps / Questa Formal Property Checking – What’s New in Functional Verification from Mentor: Session 4
by Admin on 05-27-2020 at 12:07 am

Register For This Web Seminar

Online – Jun 4, 2020
4:00 PM – 5:00 PM Europe/London

Online – Jun 4, 2020
4:00 PM – 5:00 PM US/Pacific

This is the fourth of a 5-part series on “What’s New in Functional Verification from Mentor.” Each session will be presented twice at the times shown above

Read More

CEO Interview: Adnan Hamid of Breker Systems

CEO Interview: Adnan Hamid of Breker Systems
by Daniel Nenni on 02-21-2019 at 7:00 am

Breker Verification Systems solves challenges across the functional verification process for large, complex semiconductors. This includes streamlining UVM-based testbenches for IP verification, synchronizing software and hardware tests for large system-on-chips (SoCs), and simplifying test sets for hardware emulation… Read More


Don’t Stand Between The Anonymous Bug and Tape-Out (Part 2 of 2)

Don’t Stand Between The Anonymous Bug and Tape-Out (Part 2 of 2)
by Alex Tan on 03-16-2018 at 7:00 am


The second panel is about system coverage and big data. Coverage metrics have been used to gauge the quality of verification efforts during development. At system level, there are still no standardized metrics to measure full coverage. The emergence of PSS, better formal verification, enhanced emulation and prototyping techniques… Read More


Mentor Functional Verification Study 2016

Mentor Functional Verification Study 2016
by Bernard Murphy on 09-14-2016 at 7:00 am

Periodically, Mentor commissions a user/usage survey on Functional Verification, conducted by the Wilson Research Group, then they publish the results to all of us, an act of industry good-citizenship for which I think we owe them a round of thanks. Harry Foster at Mentor is breaking down the report into a series of 15 blogs. He’s… Read More


Five Things To See at DVCon India 2016

Five Things To See at DVCon India 2016
by Daniel Payne on 09-02-2016 at 12:00 pm

DVCon is an annual Design and Verification Conference that started out in Silicon Valley, then expanded by adding India as a new location. Our semiconductor design and verification world is global in stature, so if you’re living in the region then consider registering for this event held Thursday and Friday, September Read More


Syncing Up CDC Signals in Low Power Designs

Syncing Up CDC Signals in Low Power Designs
by Ellie Burns on 12-08-2015 at 7:00 am

So far in my blog series on low power we’ve looked broadly at what’s changing in the low power verification landscape and focused on a new methodology developed by Mentor Graphics and ARM called successive refinement, which is now included in the UPF standard. Power management techniques create their own brand of clock domain crossing… Read More