WEBINARS: Boost Your Simulation and Modeling EfficiencyUnlock the full potential of your semiconductor designs…Read More
Asia Driving Electronics GrowthElectronics production in the major developed countries has…Read More
Automating Reset Domain Crossing (RDC) Verification with Advanced Data AnalyticsThe complexity of System-on-Chip (SoC) designs continues to…Read More
Verifying chip designs has always suffered from a two-pronged problem. The first problem is that actually building silicon is too expensive and too slow to use as a verification tool (when it happens, it is not a good thing and is called a “re-spin”). The second problem is that simulation is, and has always been, too slow.
When Xilinx… Read More
Article confirms market fears…
An article in the Korea Times cites sources that say Samsung will cut Semi Capex by 20% due to current oversupply and weak pricing. This is obviously a huge negative as Capex for 2016 will certainly be down significantly from 2015 given these cuts which follow on cuts by Intel and others. We can… Read More
FinFET processes provide power, performance, and area benefits over planar technologies. Yet, a vexing problem aggravated by FinFET’s is the greater local device current density, which translates to an increased concern for signal and power rail metal electromigration reliability failures. There is a critical secondary… Read More
Last Tuesday was the SEMI’s annual Strategic Materials Conference (SMC). The opening keynotes were given by Gary Patton, the CTO of GlobalFoundries, and Mark Thirsk, Managing Partner of Linx Consulting. This year it was held in the Computer History Museum (which always makes the commute interesting since you have to fight… Read More
I have written about Sidense before, but last week at the TSMC Open Innovation Platform Forum, I had a chance to hear a talk by, and have lunch with Betina Hold Director of R&D at Sidense. Here is what I learned.
Sidense has been focusing on the growing market in what they like to call the smart connected universe. It is best to think… Read More
There is an industry consensus about 28nm, the technology node is here to stay, and to stay for very long. If we except 20nm node, which by opposition will have a very short lifetime, 28nm is the last node following the economic part of Moore’s law: designing on smaller technology allows building cheaper IC when you integrate the same… Read More
I sat down for a chat with Gary Patton, the CTO of GlobalFoundries, at today’s SEMI Strategic Materials Conference where he had just given one of the keynotes (which I’ll cover another time). His family name isn’t really Patton, his grandfather’s name was Funkhauser, but his step-grandfather’s… Read More
The motivations for having a data and process management system in place for semiconductor design have existed for a long time. I am reluctant to admit it, but I remember early efforts to do this back in the 80’s at Valid Logic. Cadence was also developing this capability in house through the early 90’s. Back then designs were much … Read More
Last week at TSMC’s OIP symposium, Jen-Tai Hsu, Kilopass’s VP R&D, presented A New Solution to Sensing Scheme Issues Revealed.
See also Jen-Tai Hsu Joins Kilopass and Looks to the Future of Memories
He started with giving some statistics about Kilopass:
Displacing the Silicon Power MOSFET with eGaN® FETs
35 years ago the silicon power MOSFET was a disruptive technology that displaced the bipolar transistor – and a $12B market emerged. The dynamics of this transition taught us that there are four key factors controlling the adoption rate of a new power conversion technology:
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TSMC 16th OIP Ecosystem Forum First Thoughts